1112
8, AUGUST 2021
Improving Low-Frequency Noise in 14-nm
FinFET by Optimized High-k/Metal Gate
Thermal Processing
Hao Zhu , Bin Ye , Chengkang Tang, Xianghui Li , Qingqing Sun , and David Wei Zhang
Abstract — Low-frequency noise has become one of the
critical factors in ultra-scaled MOSFET devices, and is also
effective as an evaluating tool in characterizing device
structure and reliability. Here, the low-frequency noise
in 14 nm-FinFET is studied, and its dependence on trap
defects of high-k dielectric and interface is further experi-
mentally investigated. By using NH3 /N2 thermal processing
in high-k/metal gate (HKMG) module, the 1/f noise char-
acteristics have been greatly improved. The dominating
mechanism is quantitatively analyzed focusing on the defect
trap density in bulk HfO2 and SiO2 interface based on
the carrier number fluctuation model. Moreover, the carrier
mobility and the bias temperature instability property of the
FinFET devices are also enhanced which further confirms
the improvement in low-frequency noise upon optimized
thermal processing.
Index Terms — Low-frequency noise, thermal annealing,
FinFET, gate dielectric, reliability.
I. I NTRODUCTION
T HE continuous downscaling of MOS transistors is degrad-
ing the signal-to-noise ratio, and further device explo-
ration at advanced technology node is severely limited by the
low-frequency noise, which is inversely dependent on the gate
size. Moreover, the employment of high-k dielectric replac-
ing conventional SiO2 as the gate oxide introduces defects
between the gate and channel, and increases the low-frequency
noise due to its high defect-sensitivity. The technical challenge
to form thinner and taller fin structures in novel FinFET
can also generate defective channel/dielectric interface which
further degrades the low-frequency noise performance.
As a typical dominating low-frequency noise, the 1/ f noise
has been widely studied in solid-state electronic devices.
In addition, 1/ f noise characterization also enables a metrol-
ogy approach to evaluate gate dielectric quality as well as to
Manuscript received May 22, 2021; revised June 11, 2021 and
June 17, 2021; accepted June 18, 2021. Date of publication June 22,
2021; date of current version July 26, 2021. This work was supported in
part by the National Key Research and Development Program of China
under Grant 2018YFB2202800, in part by NSFC under Grant 61904033,
and in part by the Science and Technology Commission of Shanghai
Municipality under Grant 20501130202. The review of this letter was
arranged by Editor K. J. Kuhn. (Corresponding authors: Hao Zhu;
Qingqing Sun.)
The authors are with the State Key Laboratory of ASIC and System,
School of Microelectronics, Fudan University, Shanghai 200433, China
(e-mail: hao_zhu@fudan.edu.cn; qqsun@fudan.edu.cn).
Color versions of one or more figures in this letter are available at
https://doi.org/10.1109/LED.2021.3091488.
Digital Object Identifier 10.1109/LED.2021.3091488
0741-3106 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
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IEEE ELECTRON DEVICE LETTERS, VOL. 42, NO.
experimentally identify the defect traps in a non-destructive
manner. Various models have been theoretically proposed
seeking the origin of 1/ f noise in FinFET which provide
good guidelines to optimize the fabrication process [1]–[5].
In the gate stack of FinFET devices, the SiO2 interface
layer is typically prepared by wet chemistry. The surface
of such SiO2 interlayer more favorable to the growth of
HfO2 high-k dielectric as compared to dry oxidation. The
intrinsic defects in the wet SiO2 are suppressed by the thermal
processing after HfO2 deposition which is known as post-
dielectric annealing (PDA), but with the penalty of increasing
interlayer thickness degrading device reliability. Moreover, the
HfO2 dielectric deposited by atomic layer deposition (ALD)
is generally oxygen-deficient, and the defects of oxygen
vacancies can act as trapping centers deteriorating the 1/ f
noise characteristics. Additional thermal processing like post-
metal annealing (PMA) in the HKMG module can drive more
oxygen diffusing from HfO2 to the SiO2 interface generating
additional interface traps. This will not only further degrade
the 1/ f noise performance but also lower the BTI reliability of
the device. HfO2 -based dielectric nitridation by NH3 annealing
has been found with effective improvement in defect trap
density [6], [7]. However, there still lacks a comprehensive
analysis of the nitridation impact on the DC performance and
reliability characteristics including low-frequency noise and
BTI property based on 14-nm FinFET technology.
In this work, for the first time, we have optimized the
thermal processing in the HKMG module to improve the 1/ f
noise characteristics in 14-nm FinFET devices. By introducing
NH3 /N2 annealing after PDA, the oxygen vacancies in HfO2
are passivated and SiON is formed in the SiO2 interface layer
effectively prohibiting the oxygen diffusion. The carrier num-
ber fluctuation mechanism is quantitatively analyzed, and the
1/ f noise is significantly improved upon optimized processing
which enhances the carrier mobility and reliability of the
device at the same time.
II. D EVICE FABRICATION AND E XPERIMENTAL D ETAILS
The FinFET devices are fabricated based on the Semi-
conductor Manufacturing International Corporation (SMIC)
14-nm FinFET CMOS process platform. The length of the
20-fin channel is 240 nm for both nMOS and pMOS devices.
Fig. 1 shows the process flow of the HKMG module used
in this work. Based on the baseline process, a millisecond
annealing (MSA) in NH3 with 1.4 ms annealing time is
performed after PDA as an experimental split. 3.5% and 10%
NH3 in N2 environment are tested and compared.
ZHU et al.: IMPROVING LOW-FREQUENCY NOISE IN 14-nm FinFET
Fig. 1. Process flow of the HKMG module. The millisecond thermal
processing in NH3 is performed after PDA as an experimental split.
Fig. 2. The normalized drain current PSD as vs. frequency of (a) nMOS
and (b) pMOS devices. Numerical ratio of normalized PSD between
different process and baseline of (c) nMOS and (d) pMOS devices.
III. R ESULTS AND D ISCUSSION
Fig. 2(a) and 2(b) show the normalized drain current power
spectral density (PSD) Sid /I2d of nMOS and pMOS devices
based on the baseline and 3.5%/10% NH3 MSA treatment,
respectively. The spectra well follow the 1/ f characteristics
from 10 Hz to 100k Hz, and the PSD is clearly lowered
upon NH3 MSA processing. As shown in Fig. 2(c) and 2(d),
a maximum reduction of 37% and 45% in normalized PSD
has been achieved for nMOS and pMOS devices, respectively
by using 10% NH3 MSA processing.
According to the analysis based on the Hooge’s mobility
fluctuation (HMF) model [8] and McWhoter’s carrier number
fluctuation (CNF) model [9], the Sid /I2d can be described
as [10]:
Sid /Id2 = (gm /Id )2 × (1 +  × Id /gm )2 × Sv f b
where Svfb is the PSD of flat-band voltage fluctuation,  is the
CNF factor and gm is the device transconductance. If the 1/ f
noise is dominated by CNF, Sid /I2d is proportional to (gm /Id )2
with  = 0. Fig. 3 shows the dependence of Sid /I2d on Id for
the baseline and 10% NH3 MSA devices (nMOS and pMOS).
Sid /I2d varies with Id as (gm /Id )2 for all samples, suggesting the
dominating mechanism of CNF model in our 14-nm FinFETs.
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Fig. 3. The Sid /I2d as a function of Id (blue) and the dependence
of (gm /Id )2 on Id (red) of (a) baseline nMOS, (b) baseline pMOS,
(c) 10% NH3 MSA nMOS and (d) 10% NH3 MSA pMOS.
Fig. 4. XPS spectra of HfO2 dielectric after different thermal processing.
As mentioned above, the bulk defects of oxygen vacancies
in HfO2 dielectric as well as the interface traps at the Si inter-
layer can trap and de-trap carriers degrading the low-frequency
noise property. X-ray photoelectron spectroscopy (XPS) is
used to analyze and compare the elemental bonding char-
acteristics in HfO2 with MSA processing in N2 and NH3 .
As shown in Fig. 4, the presence of feature peaks at 395.7 eV
observed from spectra of the NH3 MSA sample indicates
formation of stable N-Hf bonds. The atomic concentration
of N in HfO2 is 2.0% and 2.7% with 3.5% and 10% NH3
MSA, respectively. The introduction of N atoms in HfO2
can compensate the oxygen vacancies and suppress the bulk
trap density in the gate dielectric, and thus, improve the 1/ f
noise performance. It should be noted that a shoulder peak at
396.7 eV is also observed which is ascribed to the of N-Si
bonding at the SiO2 interlayer [11]. Such N atom diffusion
to the SiO2 interlayer is favorable for the formation of SiON
(1) which not only increases the permittivity of SiO2 interlayer,
but also functions as a barrier prohibiting oxygen diffusion to
the interlayer in subsequent thermal processing.
We then characterize the influence of bulk oxide traps on
the 1/ f noise with different thermal processing based on CNF
model. To extract the oxide trap density (Not ), we rewrite
Eq. (1) as:
 √ √
(S id /Id2 ) = S v f b × gm /Id +  × S v f b (2)
1114
 under different processing conditions. (b) Effective mobility of nMOS
Fig. 5. Linear fitting of (Sid /Id2 ) to gm /Id of (a) nMOS and (b) pMOS
devices. Frequency is 10k Hz. Extracted bulk trap density as a function
of trap depth of (c) nMOS and (d) pMOS devices. Data obtained at
frequency of 10 Hz to 100k Hz were used.
√ processing. This is consistent with reported results that gate
S v f b can be extracted as the slope from the linear fitting
of (S id /Id2 ) to gm /Id under different gate voltage, which
is shown in Fig. 5(a) and 5(b). Thus, Not can be further
calculated by:
Sv f b = (q 2 kT λNot )/(W LC O
2 ened by Coulomb scattering at the oxygen vacancies. By using
X f) (3)
where λ is the oxide tunneling attenuation factor, Cox is the
gate capacitance per unit area, f is the frequency, W and L are
the channel width and length, respectively. At 10k Hz, Not is
decreased from 1.0 × 1018 to 6.8 × 1017 for nMOS and from
7.0 × 1018 to 4.1 × 1018 for pMOS after 10% NH3 MSA,
respectively.
Furthermore, the depth distribution (xt ) of the bulk traps
in HfO2 can be evaluated from the noise level at various
frequency according to xt = λln(1/2π f τ0 ), where τ0 is the
Shockley-Read-Hall recombination time with a typical value
of 10−10 s [12]. By assuming Not as the trapping centers based
on the carrier number fluctuation mechanism, the distribution
of trap density in HfO2 dielectric can be estimated by plotting
the calculated Not versus xt for nMOS and pMOS, which
are shown in Fig. 5(c) and 5(d), respectively. It is found that
despite the much lowered Not after NH3 annealing, the peak
trap density in the baseline sample is located at 1.2 ∼ 1.4 nm
depth, while it is closer to the SiO2 interlayer in the MSA
treated samples. It is worth to mention that the dielectric bulk
trap density is higher in pMOS than that in nMOS devices
as shown in Fig. 4. This is because more electrons tend to
transfer to the metal gate in pMOS due to the higher metal
work function, and more oxygen vacancies are left behind
leading to flat-band voltage shift which is known as the Fermi-
level pinning effect [13].
In addition to the HfO2 bulk traps, the interface states
at the SiO2 interlayer can also contribute to the carriers
trapping and de-trapping. By introducing thermal process-
ing in NH3 , the interface trap density (Nit ) extracted by
charge-pumping method is lowered for both nMOS and
pMOS devices (Fig. 6(a)). Fig. 6(a) also indicates that the
inversion layer thickness (Tinv ) decreases with NH3 MSA
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IEEE ELECTRON DEVICE LETTERS, VOL. 42, NO. 8, AUGUST 2021
Fig. 6. (a) Extracted interface trap density and inversion layer thickness
and pMOS FinFET devices with and without 10% NH3 MSA annealing.
(c) nMOS PBTI and (d) pMOS NBTI reliability of the devices at 125 ◦ C
using baseline and 10% NH3 MSA processing. Vg is 1.5 V.
stack nitridation with small thermal budget (like MSA used
here) can lower the Nit and Tinv due to the formation of
SiON barrier at the SiO2 /HfO2 interface after NH3 thermal
processing [14], [15]. Based on the above results, we further
characterized the carrier mobility which can be easily damp-
split C-V measurement, the calculated effective mobility is
plotted in Fig. 6(b) which demonstrates enhancement with
NH3 MSA processing due to the minimizing of defective
trapping centers. Fig. 6(c) and 6(d) show the BTI reliability
characterization results. Five devices located at different sites
on the wafer are selected for each process condition. With
10% NH3 MSA processing, it is observed that the interface
trap-dominated pMOS NBTI degradation [16] is suppressed
with smaller threshold voltage Vt shift (Fig. 6(c)). On the
other hand, the nMOS PBTI affected by the oxygen vacancies
in HfO2 dielectric is also improved with less electron trap-
ping and de-trapping. Such results are well aligned with the
improvement in 1/ f noise illustrating effective optimization
in device structure and electrical performance with engineered
thermal processing.
IV. C ONCLUSION
In summary, improved 1/ f noise characteristics have been
achieved in 14-nm FinFET devices through optimized thermal
processing. By introducing MSA in NH3 environment after
PDA in HKMG module, N atoms are successfully doped in the
HfO2 dielectric to compensate the oxygen vacancies lowing
the bulk trap density. Meanwhile, such thermal processing also
forms a SiON layer at the SiO2 interface which effectively
prohibits oxygen diffusion from HfO2 to the substrate. This
not only lowers the oxygen vacancies trap density in the bulk
HfO2 , but also minimize the growth of the SiO2 interlayer as
well as the interface trap density. The 1/ f noise performance
is thus enhanced based on the CNF model and the device
performance including the mobility and BTI reliability is also
improved. This provides a promising pathway for the device
study and process optimization in advanced semiconductor
technology nodes.
ZHU et al.: IMPROVING LOW-FREQUENCY NOISE IN 14-nm FinFET
R EFERENCES
[1] A. V. de Oliveira, D. Xie, H. Arimura, G. Boccardi, N. Collaert,
C. Claeys, N. Horiguchi, and E. Simoen, “Low-frequency noise
characterization of germanium n-channel FinFETs,” IEEE Trans.
Electron Devices, vol. 67, no. 7, pp. 2872–2877, Jul. 2020, doi:
10.1109/TED.2020.2990714.
[2] P. Kushwaha, H. Agarwal, Y.-K. Lin, A. Dasgupta, M.-Y. Kao, Y. Lu,
Y. Yue, X. Chen, J. Wang, W. Sy, F. Yang, P. C. Chidambaram,
S. Salahuddin, and C. Hu, “Characterization and modeling of flicker
noise in FinFETs at advanced technology node,” IEEE Elec-
tron Device Lett., vol. 40, no. 6, pp. 985–988, Jun. 2019, doi:
10.1109/LED.2019.2911614.
[3] C. G. Theodorou, N. Fasarakis, T. Hoffman, T. Chiarella, G. Ghibaudo,
and C. A. Dimitriadis, “Origin of the low-frequency noise in n-channel
FinFETs,” Solid-State Electron., vol. 82, pp. 21–24, Apr. 2013, doi:
10.1016/j.sse.2013.01.009.
[4] R. Talmat, H. Achour, B. Cretu, J.-M. Routoure, A. Benfdila,
R. Carin, N. Collaert, A. Mercha, E. Simoen, and C. Claeys, “Low
frequency noise characterization in n-channel FinFETs,” Solid-State
Electron., vol. 70, pp. 20–26, Apr. 2012, doi: 10.1016/j.sse.2011.
11.007.
[5] J. Woo Lee, M. ju Cho, E. Simoen, R. Ritzenthaler, M. Togo,
G. Boccardi, J. Mitard, L.-Å. Ragnarsson, T. Chiarella, A. Veloso,
N. Horiguchi, A. Thean, and G. Groeseneken, “1/f noise analysis
of replacement metal gate bulk p-type fin field effect transistor,”
Appl. Phys. Lett., vol. 102, no. 7, Feb. 2013, Art. no. 073503, doi:
10.1063/1.4793306.
[6] M. S. Akbar, H.-J. Cho, R. Choi, C. S. Kang, C. Y. Kang, C. H. Choi,
S. J. Rhee, Y. H. Kim, and J. C. Lee, “Optimized NH3 annealing
process for high-quality HfSiON gate oxide,” IEEE Electron Device
Lett., vol. 25, no. 7, pp. 465–467, Jul. 2004, doi: 10.1109/LED.2004.
830270.
[7] P. Srinivasan, E. Simoen, Z. M. Rittersma, W. Deweerd, L. Pantisano,
C. Claeys, and D. Misra, “Effect of nitridation on low-frequency (1/f)
noise in n- and p-MOSFETs with HFO2 gate dielectrics,” J. Elec-
trochem. Soc., vol. 153, no. 9, pp. G819–G825, Jul. 2006, doi:
10.1149/1.2216455.
Authorized licensed use limited to: UNIVERSITY SABAH MALAYSIA. Downloaded on August 28,2021 at 04:15:02 UTC from IEEE Xplore. Restrictions apply.
1115
[8] F. N. Hooge, “1/f noise sources,” IEEE Trans. Electron Devices, vol. 41,
no. 11, pp. 1926–1935, Nov. 1994, doi: 10.1109/16.333808.
[9] A. L. McWhorter and R. H. Kingston, Semiconductor Surface Physics.
Philadelphia, PA, USA: Univ. of Pennsylvania Press, 1957.
[10] G. Ghibaudo, O. Roux, C. Nguyen-Duc, F. Balestra, and J. Brini,
“Improved analysis of low frequency noise in field-effect MOS tran-
sistors,” Phys. Status Solidi A, vol. 124, no. 2, pp. 571–581, Apr. 1991,
doi: 10.1002/pssa.2211240225.
[11] M. Dai, J. Liu, D. Guo, S. Krishnan, J. F. Shepard, P. Ronsheim,
U. Kwon, S. Siddiqui, R. Krishnan, Z. Li, K. Zhao, J. Sudijono, and
M. P. Chudzik, “A novel atomic layer oxidation technique for EOT
scaling in gate-last high-κ/metal gate CMOS technology,” in IEDM Tech.
Dig., Dec. 2011, pp. 28.5.1–28.5.4, doi: 10.1109/IEDM.2011.6131632.
[12] J. W. Lee, W. S. Yun, and G. Ghibaudo, “Impact of trap localization
on low-frequency noise in nanoscale device,” J. Appl. Phys., vol. 115,
no. 19, May 2014, Art. no. 194501, doi: 10.1063/1.4878456.
[13] Y. Akasaka, G. Nakamura, K. Shiraishi, N. Umezawa, K. Yamabe,
O. Ogawa, M. Lee, T. Amiaka, T. Kasuya, H. Watanabe, T. Chikyow,
F. Ootsuka, Y. Nara, and K. Nakamura, “Modified oxygen vacancy
induced Fermi level pinning model extendable to P-metal pinning,”
Jpn. J. Appl. Phys., vol. 45, no. 49, pp. L1289–L1292, Dec. 2006, doi:
10.1143/JJAP.45.L1289.
[14] H. Arimura, K. Wostyn, L.-A. Ragnarsson, E. Capogreco, A. Chasin,
T. Conard, S. Brus, P. Favia, J. Franco, J. Mitard, S. Demuynck,
and N. Horiguchi, “Ge oxide scavenging and gate stack nitrida-
tion for strained Si0.7 Ge0.3 pFinFETs enabling 35% higher mobility
than Si,” in IEDM Tech. Dig., Dec. 2019, pp. 29.2.1–29.2.4, doi:
10.1109/IEDM19573.2019.8993467.
[15] Y. He, D. W. Zhang, H. Liu, Y. Chen, G. Yu, Y. He, L. Jin, J. Wu,
J. Zhao, W. Song, S. Yu, and J. Wu, “Investigation of different post HK
annealing impact on HK film property and device performance,” in Proc.
20th Int. Conf. Ion Implantation Technol. (IIT), Jun. 2014, pp. 1–4, doi:
10.1109/IIT.2014.6939969.
[16] E. Cartier, A. Kerber, T. Ando, M. M. Frank, K. Choi, S. Krishnan,
B. Linder, K. Zhao, F. Monsieur, J. Stathis, and V. Narayanan, “Fun-
damental aspects of HfO2 -based high-k metal gate stack reliability
and implications on tinv-scaling,” in IEDM Tech. Dig., Dec. 2011,
pp. 18.4.1–18.4.4, doi: 10.1109/IEDM.2011.6131579.