QUESTION BANK FOR VLSI LAB

1. Write a behavioral verilog code for buffer and perform simulation using
testbench program and synthesize the design and generate the report.

2. Draw the schematic design of the common source and perform following
analysis
a) Transient analysis
b) DC analysis

3. Write a structural verilog code for transmission gate and perform

simulation using testbench program
4.
5. Draw schematic design for inverter and perform following analysis

a) Transient analysis
b) DC analysis

6. Write verilog code for 4-bit serial adder and perform simulation using
testbench program and synthesize the design and generate the report

7. Draw schematic design for inverter and perform following analysis

a) Transient analysis
b) DC analysis
8. Write verilog code for 4 bit parallel adder and perform simulation using
testbench program and synthesize the design and generate the report.

9. Draw the schematic design for common drain amplifier and perform
following analysis

a) Transient analysis
b) DC analysis

10. Write verilog code for JK flip flop and perform simulation using testbench
program and synthesize the design and generate the report.

11. Draw the schematic design for common drain amplifier and perform
following analysis

a) Transient analysis
b) DC analysis

12.Write verilog code for Master –slave JK flip flop and perform simulation
using testbench program and synthesize the design and generate the report

13. Draw the schematic design for inverter and perform following analysis

a) Transient analysis
b) DC analysis
14.Write verilog code for 4-bit Asynchronous counter and perform simulation
using testbench program and synthesize the design and generate the
report.

15. Draw schematic design for inverter and perform following analysis

a) Transient analysis
b) DC analysis

16.Write verilog code for D flip flop and perform simulation using testbench
program and synthesize the design and generate the report.

17. Draw the schematic design for operational amplifier and perform following
analysis

a) Transient analysis
b) DC Analysis

18.Write verilog code for SR flip flop and perform simulation using testbench
program and synthesize the design and generate the report.

19. Draw the schematic design of the common source amplifier and perform
the following analysis

a) Transient analysis
b) DC Analysis
20.Write verilog code for successive approximation register and perform
simulation using testbench program and synthesize the design and
generate the report.

21. Draw the layout for common drain amplifier and obtain voltage versus
time and voltage versus voltage characteristics.

22.Write a behavioral code for D flip and perform simulation using testbench
program and synthesize the design and generate the report

23. Draw the layout for4 bit R- 2R Digital to Analog converter and obtain the
voltage Versus time characteristics and compare with calculated analog
values.

24.Write verilog code for inverter and perform simulation using testbench
program and synthesize the design and generate the report.

25. Draw the layout for4 bit R- 2R Digital to Analog converter and obtain the
voltage Versus time characteristics and compare with calculated analog
values.