Date – 28/07/2021

Name -sankhadeep Chakrabarti

UnIversity roll - 12100119111
University Registration no- 018324.
Stream-Computer science
engineerin(B).
Year – 2019-2023
Semester – 4th
Paper name- Computer architecture lab.
Paper code – pcc-cs492.

Q 4. A) Write a program to design and simulate Half

Subtractor.
VHDL CODE:
DESIGN:
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity half_sub is
port( a,b : IN std_logic;
diff,borrow : OUT std_logic);
end half_sub;

architecture dataflow of half_sub is

begin

diff <= a xor b;

borrow <= (not a) and b;

end dataflow;

TEST BENCH:
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

entity half_sub_tb is
end entity;

architecture tb of half_sub_tb is
component half_sub is
port(a,b : IN std_logic;
diff,borrow : OUT std_logic);
end component;

signal a,b,diff,borrow : std_logic;

begin

uut: half_sub port map(

a => a, b => b,
diff => diff,
borrow => borrow);

stim: process
begin

a <= '0';
b <= '0';
wait for 20 ns;

a <= '0';
b <= '1';
wait for 20 ns;

a <= '1';
b <= '0';
wait for 20 ns;

a <= '1';
b <= '1';
wait for 20 ns;
wait;

end process;

end tb;

OUTPUT :

…………………………………………………………………………………………………
…………………………………………………………………………………………………
……………………

Q 4.B) Write a program to design and simulate Full

Subtractor using structural type of coding.
VHDL CODE:
DESIGN :
-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;
entity full_sub is
port( a,b,c : IN std_logic;
diff,borrow : OUT std_logic);
end full_sub;

architecture dataflow of full_sub is

begin

diff <= (a xor b) xor c;

borrow <=((not a) and (b or c)) or (b and c);

end dataflow;

TEST BENCH:
-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

entity full_sub_tb is
end entity;

architecture tb of full_sub_tb is
component full_sub is
port(a,b,c : IN std_logic;
diff,borrow : OUT std_logic);
end component;

signal a,b,c,diff,borrow : std_logic;

begin

uut: full_sub port map(

a => a, b => b,
c => c,
diff => diff,
borrow => borrow);

stim: process
begin

a <= '0';
b <= '0';
c <= '0';
wait for 20 ns;

a <= '0';
b <= '0';
c <= '1';
wait for 20 ns;

a <= '0';
b <= '1';
c <= '0';
wait for 20 ns;

a <= '0';
b <= '1';
c <= '1';
wait for 20 ns;
wait;

end process;

end tb;

OUTPUT:
…………………………………………………………
…………………………………………………………
…………….