DICA Lab Manual R16 2019

DIGITAL IC APPLICATIONS LAB
EX PT NO : 1 DATE :
LOGIC GATES
AIM: To verify and simulate the logic gates using VHDL.
APPARATUS REQUIRED:
 Xilinx ISE Design Suite 14.7 Software

 Personal Computer
THOERY:
Logic gates are the basic elements that make up a digital system. The gate is a digital circuit with
one or more inputs, but only one output. By connecting the different gates in different ways, we can
build circuits that perform arithmetic and other functions.
The operation of a logic gate can be easily understood with the help of “truth table”. A truth table is
a table that shows all the input-output possibilities of a logic circuit ie., the truth table indicates the
outputs for different possibilities of the inputs. The types of gates available are the AND, OR, NOT,
NAND, NOR, exclusive-OR and the exclusive-NOR. Except for the exclusive-NOR gate they are
available in monolithic integrated form.
AND gate: The AND gates has two or more inputs. It performs a logical multiplication. The output
is HIGH (1), when both the inputs are 1; otherwise the output from the gate is LOW (0). The output
from the AND gate is written as A.B.
OR gate: The OR gates has two or more inputs. It performs a logical addition. The output is HIGH
(1), if any of the inputs are 1; the output is LOW (0) if and only if all the inputs are 0. The output
from the OR gate is written as A+B.
NOT gate: The NOT gate has only one input. It performs a basic logic function called inversion.
The output is HIGH (1), when the input is 0; the output is LOW (0) when the input is 1. The output
from the NOT gate is written as A’.
NAND gate: The NAND gate is a contraction of AND-NOT. It has two or more inputs. The output
is HIGH (1), when any of the inputs are 0; the output is LOW (0), if and only if all the inputs are 1.
The output from the AND gate is written as (A.B)’. It is a universal gate.
SIETK, ECE Page |1

NOR gate: The NOR gate is a contraction of OR-NOT. It has two or more inputs. The output is
HIGH (1), when all inputs are 0; the output is LOW (0),when any of the inputs are 1. The output
from the AND gate is written as (A+B)’. It is a universal gate.
AND gate:
OR gate:
SIETK, ECE Page |2

NOT gate:
NAND gate:
SIETK, ECE Page |3

NOR gate:
PROGRAMS:
2-INPUT NAND GATE:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY NAND_gate IS
port(a:in std_logic;
b:in std_logic;
c:out std_logic);
END NAND_gate ;
ARCHITECTURE dataflow OF NAND_gate IS

BEGIN
c<= a nand b;
END dataflow;
2-INPUT NOR GATE:

LIBRARY ieee;
ENTITY NOR_gate IS
port(a,b:in std_logic;
SIETK, ECE Page |4

c:out std_logic);
END NOR_gate ;
ARCHITECTURE dataflow OF NOR_gate IS

BEGIN
c<=a nor b;
END dataflow;
2-INPUT AND GATE:
LIBRARY ieee;
ENTITY and_gate IS
c: out std_logic);
END and_gate ;
ARCHITECTURE dataflow OF and_gate IS

BEGIN
c<= a and b;
END dataflow;
2-INPUT OR GATE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
entity orgate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end orgate;
architecture Behavioral of orgate is

begin
c<= a or b;
end Behavioral;
2-INPUT EX-OR GATE:
LIBRARY ieee;
ENTITY exor_gate IS
SIETK, ECE Page |5
c:out std_logic);
END exor_gate ;
ARCHITECTURE dataflow OF exor_gateIS

BEGIN
c<=a xor b;
END dataflow;
2-INPUT EX-NOR GATE:
LIBRARY ieee;
ENTITY exnor_gate IS
c:out std_logic);
END exnor_gate ;
ARCHITECTURE dataflow OF exnor_gate IS

BEGIN
c<=not(a xor b);
END dataflow;
NOT GATE:
LIBRARY ieee;
ENTITY not_gate IS
port(a:in std_logic;
b:out std_logic);
END not_gate;
ARCHITECTURE dataflow OF not_gate IS

BEGIN
b<=not a;
END dataflow;
PROCEDURE:
1. Select File > New Project. The New Project Wizard appears.
2. First, enter a location (directory path) for the new project, then give a name for the project.
3. Select HDL from the Top-Level Module Type list, indicating that the top-level file in your
project will be HDL, rather than Schemetic or other stuffs.
4. Click on Next to move to the project properties page.
Fill in the properties in the table as shown below:

SIETK, ECE Page |6
Device Family: Spartan3E
Device: XCES100E
Package: VQ100
Speed: -5
Synthesis Tool: XST [VHDL/Verilog]
Simulator: ISE Simulator [VHDL/Verilog]
Preferred Language: VHDL
5. Click Next to proceed to the Create New Source window in the New Project Wizard. At the
end of the next section, your new project will be created.
6. Click New Source in the New Project Wizard to add to one new source to your project.,
Type in the file name. Select VHDL Module as the source type in the New Source Dialog
box.
7. Verify that the Add to Project checkbox is selected and click Next. Define the ports for
your VHDL source.
8. Click Next in the Define Module dialog box. Click Finish in the New Project Wizard -
Summary dialog box to complete the new source file template.
9. ISE creates and displays the new project in the Source in Project window and adds
the counter.vhd file to the project. Save the file by selecting File -> Save.
10. Click + next to the Synthesize-XST process to expand the hierarchy. Double-click on
the Synthesize -XST process.
11. You must correct any errors found in your source files. If you continue without valid syntax,
you will not be able to simulate or synthesize your design.
12. Select the Behavioral Simulation in the Source window. Double-click on the Simulate
Behavioral Model process in the Project window. The ISE Simulator opens and run the
simulation to the end of the test bench.
PRECAUTIONS:
1. Create project with appropriate file name (preferably lowercase).
2. File name of the project should not consists of any whitespace or special characters.
3. Do not use the keywords as a VHDL source file name.
4. Type the program in lowercase preferably.
5. Check syntax before simulating.
6. Check proper print setting before taking printout of simulated waveforms.
SIETK, ECE Page |7

SIMULATED WAVEFORMS:
RESULT:
VIVA QUESTIONS:
1. What are the advantages of VHDL?
2. Implement the following function using VHDL code f=AB+CD.
3. Define the logic gates.
4. What are the different types of logic gates?
SIETK, ECE Page |8

EX PT NO :2 DATE :
HALF ADDER, HALF SUBTRACTOR, FULL ADDER, FULL SUBTRACTOR
AND RIPPLE CARRY ADDER
AIM: To verify and simulate the truth tables of combinational circuits by using VHDL.
APPARATUS REQUIRED:
 Xilinx ISE Design Suite 14.7 software
 Personal Computer
THEORY:
Half Adder: A half-adder is a combinational circuit that can be used to add two binary bits. It has
two inputs that represent the two bits to be added and two outputs, with one producing the SUM
output and the other producing the CARRY. The Sum can be applied using EX-OR gate, carry
output can be applied using an AND gate.
Full Adder: A full adder is a combinational circuit that forms the arithmetic sum of three input bits.
It consists of 3 inputs and 2 outputs. Two of the input variables, represent the significant bits to be
added. The third input represents the carry from previous lower significant position. The logic
diagram of the full adder can also be implemented with two half-adders and one OR gate. The S
output from the second half adder is the exclusive-OR of Cin and the output of the first half-adder.
Half subtractor: The Half-Subtractor is a combinational circuit which is used to perform

subtraction of two bits. It has two inputs, X(minuend) and Y(subtrahend) and two outputs D
(difference) and B (borrow).
SIETK, ECE Page |9

HALF ADDER:
TRUTH TABLE: K- MAP SIMPLIFICATION:
Inputs Outputs
A B Carry (C) Sum (S)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
LOGIC DIAGRAM:
FULL ADDER:
TRUTH TABLE:
Inputs Outputs
A B Cin Sum (S) Carry (Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
SIETK, ECE P a g e | 10
K-MAP SIMPLIFICATION:
LOGIC DIAGRAM:
FULL ADDER:
FULL ADDER USING TWO HALF ADDERS:
HALF-SUBTRACTOR :
Logic Diagram Functional Table
FULL-SUBTRACTOR :
Logic Diagram Functional Table
RIPPLE CARRY ADDER:
TRUTH TABLE:
PROGRAMS:
HALF ADDER:
LIBRARY ieee;
ENTITY halfadder IS
port(a,b: in std_logic;
sum,carry:out std_logic);
END halfadder ;
ARCHITECTURE dataflow OF halfadder IS

BEGIN
sum<= a xor b;
carry<=a and b;
END dataflow;
HALF SUBTRACTOR:
LIBRARY ieee;
ENTITY halfsubtractor IS
borrow,difference:out std_logic);
END halfsubtractor ;
ARCHITECTURE dataflow OF halfsubtractor IS

BEGIN
difference<= a xor b;
borrow<=(not a)and b;
END dataflow;
FULL ADDER:
LIBRARY ieee;
ENTITY fulladder IS
port(a,b,c:in std_logic;
sum,carry:out std_logic);
END fulladder ;
ARCHITECTURE dataflow OF fulladder IS

BEGIN
sum<=a xor b xor c;
carry<=(a and b) or (a and c) or (b and c);
END dataflow;
FULL SUBTRACTOR:
LIBRARY ieee;
ENTITY fullsubtractor IS
port(a,b,c:in std_logic;
difference,borrow:out std_logic);
END fullsubtractor ;
ARCHITECTURE dataflow OF fullsubtractor IS

BEGIN
difference<=a xor b xor c;
borrow<=(b and c) or ((not a) and c) or ((not a) and b);
END dataflow;
RIPPLE CARRY ADDER:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_ arith.all;
entity RCA is
port(a, b : in std_logic_vector(3 downto 0); cout : out std_logic;
sum : out std_logic_vector(3 downto0));
end entity RCA;
architecture struct_RCA of RCA is

signal cin: std_logic_vector(3 downto 0);
component FA is
port(a, b : in std_logic; cin : in std_logic;
cout : out std_logic; sum : out std_logic);
end component;
begin
cin(0) <= ‘0’;
FA0 : FA port map(a(0), b(0), cin(0), cin(1), sum(0));
FA3 : FA port map(a(3), b(3), cin(3), cout, sum(3));
end architecture struct_RCA;
PROCEDURE:

Device: XCES100E
Package: VQ100
Speed: -5
box.
your VHDL source.
PRECAUTIONS:

HALF ADDER
HALF SUBTRACTOR
FULL ADDER
FULL SUBTRACTOR
RESULT:
VIVA QUESTIONS:
1. What are the applications of half adder, half subtractor, full adder, full subtractor & ripple
carry adder?
2. Draw the half adder, half subtractor, full adder, full subtractor & ripple carry adder logic
diagrams.
3. What is the difference between half adder and full adder?
EXPT NO: 3 DATE:

3x8 DECODER -74138 & 8x3 ENCODER- 74X148
AIM: To verify and simulate the truth tables of Encoder & Decoder circuits using VHDL.
APPARATUS REQUIRED:
 Personal computer
THEORY:
Encoder:
An encoder is a digital circuit that performs inverse operation of a decoder. An encoder has 2n input
lines and ‘n’ output lines. In encoder the output lines generates the binary code corresponding to the
input value. In octal to binary encoder it has eight inputs, one for each octal digit and three output
that generates the corresponding binary code. In encoder it is assumed that only one input has a
value of one at any given time otherwise the circuit is meaningless. It has an ambiguila that when all
inputs are zero the outputs are zero. The zero outputs can also be generated when D0=1.
Decoder:
A decoder is a multiple output logic circuit which converts input into coded output where
input and output codes are different. The input code generally has few bits than the output
code.Each input code word produces a different output code word i.e., there is one to one mapping
can be expressed in truth table.In block diagram of decoder circuit the encoded information is
present as n input producing 2n possible outputs. The 2n output values are from 0 through out 2n-1.
LOGIC DIAGRAMS
3X8 DECODER:
8x3 ENCODER:
TRUTH TABLE:
3X8 DECODER:
Enable inputs Encoded inputs Decoded
S.No
g1 g2a_l g2b_l A B C output
1 0 X X X X X 11111111
2 1 1 X X X X 11111111
3 1 X 1 X X X 11111111
4 1 0 0 0 0 0 01111111
5 1 0 0 0 0 1 10111111
6 1 0 0 0 1 0 11011111
7 1 0 0 0 1 1 11101111
8 1 0 0 1 0 0 11110111
9 1 0 0 1 0 1 11111011
10 1 0 0 1 1 0 11111101
11 1 0 0 1 1 1 11111110
8X3 ENCODER
INPUTS OUTPUTS
D7 D6 D5 D4 D3 D2 D1 D0 Q2 Q1 Q0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1
PROGRAMS:
3X8 DECODER
LIBRARY ieee;
ENTITY DECODER IS
port(G1:in std_logic;G2:in std_logic;
A:in std_logic_vector(2 downto 0);
Y:out std_logic_vector(0 to 7));
END DECODER ;
ARCHITECTURE DECODER_DFT OF DECODER IS

signal Y1:std_logic_vector(0 to 7);
BEGIN
with A select Y1<="01111111" when "000",
"10111111" when "001",
"11011111" when "010",
"11101111" when "011",
"11110111" when "100",
"11111011" when "101",
"11111101" when "110",
"11111110" when "111",
"11111111" when OTHERS;
Y<=Y1 when(G1 =’1’and G2=’0’ )
else "11111111";
END DECODER_DFT;
8X3 ENCODER:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ENCODER8_3 IS
PORT ( ENABLE: IN STD_LOGIC;
D_IN: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Q_OUT: OUT STD_LOGIC_VECTOR(2 DOWNTO 0) );
END ENCODER8_3;
ARCHITECTURE ENCODER_ARCH OF ENCODER8_3 IS
BEGIN
PROCESS(ENABLE,D_IN)
BEGIN
IF ( ENABLE = '1') THEN
D_OUT <= "000";
ELSE
CASE D_IN IS
WHEN "00000001" => Q_OUT <= "000";
WHEN "0000001X " => Q_OUT <= "001";
WHEN "000001XX " => Q_OUT <= "010";
WHEN "00001XXX " => Q_OUT <= "011";
WHEN "0001XXXX " => Q_OUT <= "100";
WHEN "001XXXXX " => Q_OUT <= "101";
WHEN "01XXXXXX" => Q_OUT <= "110";
WHEN "1XXXXXXX" => Q_OUT <= "111";
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END ENCODER_ARCH;
PROCEDURE:

Device: XCES100E
Package: VQ100
Speed: -5
box.
your VHDL source.
PRECAUTIONS:
3X8 DECODER
8X3 ENCODER:
RESULT:
VIVA QUESTIONS:
1. Define Priority Encoder.
2. How many decoders are needed to construct 4X16 decoder?
3. What is the difference between decoder and encoder?
4. What is the role of an encoder in communication?
5. What is the advantage of using an encoder?
6. List the applications of encoder & decoder.
EXPT NO:4 DATE:
8 X 1 MULTIPLEXER -74X151 & 1X4 DEMULTIPLEXER-74X155
AIM: To verify and simulate the operation of multiplexer and demultiplexer circuits using VHDL.
APPARATUS REQUIRED:
THEORY:
Multiplexer: Multiplexer means transmitting a large number of information units over a small
number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally there are 2 n input line and ‘n’
selection lines whose bit combination determine which input is selected. It is called as data selector,
because the output depends on the input data bit that is selected.
Demultiplexer: The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this reason, the
demultiplexer is also known as a data distributor. Decoder can also be used as Demultiplexer. In
the 1:4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines
enable only one gate at a time and the data on the data input line will pass through the selected gate
to the associated data output line.
LOGIC DIAGRAM:
8x1 MULTIPLEXER 74151
2X4 DEMULTIPLEXER 74155:
TRUTH TABLES:
S.No en_l Data select lines Output
Y
A B C
1 0 0 0 0 I(0)
2 0 0 0 1 I(1)
3 0 0 1 0 I(2)
4 0 0 1 1 I(3)
5 0 1 0 0 I(4)
6 0 1 0 1 I(5)
7 0 1 1 0 I(6)
8 0 1 1 1 I(7)
9 1 X X X 0
2X4 DEMULTIPLEXER 74155
PROGRAMS:
8X1 MULTIPLEXER 74151
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity mux151 is
port (
I :in STD_LOGIC_VECTOR (7 downto 0); --8 i/p lines
S :in STD_LOGIC_VECTOR (2 downto 0); --3 data select lines
en_l:in STD_LOGIC; --active low enable i/p
y :out STD_LOGIC --output line
);
end mux151;
architecture mux151 of mux151 is
begin
process (I,s,en_l)
begin
if en_l='0' then
case s is
when "000" => y <= I(0);
when "001" => y <= I(1);
when "010" => y <= I(2);
when "011" => y <= I(3);
when "100" => y <= I(4);
when "101" => y <= I(5);
when "110" => y <= I(6);
when "111" => y <= I(7);
when others=>null;
end case;
else y <= '0'; --y=0 when en_l=1
end if;
end process;
end mux151

LIBRARY ieee;
ENTITY demux IS
port(A:in std_logic_vector(1 downto 0);
C2: in std_logic;
G2: in std_logic;
2 y:out std_logic_vector(0 to 3));
END demux ;
-- A : select line
-- G2 : Strobe input
ARCHITECTURE behavioral OF demux IS

signal 2Y1 : std_logic_vector(0 to 3);
BEGIN
process(C2,G2,A)
begin
2Y1<="1111";
if A="00" then 2Y1(0)<=data;
elsif A="01" then 2Y1(1)<=data;
end if;
end process;
2y<=2Y1when G2 ='0' else "1111";
END behavioral;
PROCEDURE:

Device: XCES100E
Package: VQ100
Speed: -5
box.
your VHDL source.
PRECAUTIONS:
RESULT:
VIVA QUESTIONS:
1. What is meant by multiplexer?
2. How many 8X1 multiplexers are needed to construct 16X1 multiplexer?
3. Compare decoder with demultiplexer?
4. Design a full adder using 8X1 multiplexer?
5.List the applications of multiplexer and demultiplexer.
EXPT NO : 5 DATE :
4 BIT COMPARATOR-74X85
AIM: To verify and simulate the operation of magnitude comparator using VHDL.
APPARATUS REQUIRED:
THEORY:
A magnitude comparator is a combinational circuit that compares two given numbers (A and B)
and determines whether one is equal to, less than or greater than the other. The output is in the form
of three binary variables representing the conditions A = B, A>B and A<B, if A and B are the two
numbers being compared.
The binary variable (A=B) is equal to 1 only if all pairs of digits of the two numbers are equal.To
determine if A is greater than or less than B, we inspect the relative magnitudes of pairs of
significant bits starting from the most significant bit. If the two digits of the most significant position
are equal, the next significant pair of digits is compared. The comparison process is continued until
a pair of unequal digits is found. It may be concluded that A>B, if the corresponding digit of A is 1
and B is 0. If the corresponding digit of A is 0 and B is 1, we conclude that A<B. Therefore, we can
derive the logical expression of such sequential comparison by the following two Boolean functions,
(A>B) = A1B1′ +X1A0B0′

(A<B) = A1′B1 +X1A0′B0
The symbols (A>B) and (A<B) are binary output variables that are equal to 1 when A>B or A<B,
respectively.
LOGIC DIAGRAMS:
4-BIT COMPARATOR:
TRUTHTABLE:
Present input
Cascade
S.No. condition AGTBOUT AEQBOUT ALTBOUT
inputs
A>B A=B A<B
1 AGTBIN=1 X X X 1 0 0
1 0 0 1 0 0
2 AEQBIN=1 0 1 0 0 1 0
0 0 1 0 0 1
3 ALTBIN=1 X X X 0 0 1
PROGRAM:
library IEEE;
use IEEE.std_logic_arith.all;
entity comp is
port (
altbin: in STD_LOGIC;
aeqbin: in STD_LOGIC;
agtbin: in STD_LOGIC;
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
agtbout: out STD_LOGIC;
aeqbout: out STD_LOGIC;
altbout: out STD_LOGIC);
end comp;
architecture comp of comp is
begin
process(a,b,agtbin,aeqbin,altbin)
begin
agtbout<='0'; --initializes the outputs to ‘0’
aeqbout<='0';
altbout<='0';
if aeqbin='1' then
if a=b then aeqbout<='1';
elsif a>b then agtbout<='1';
elsif (a<b) then altbout<='1';
end if;
elsif (altbin/=agtbin)then
agtbout<=agtbin;
altbout<=altbin;
end if;
end process ;
end Comp;
PROCEDURE:

Device: XCES100E
Package: VQ100
Speed: -5
box.
your VHDL source.
PRECAUTIONS:
SIMULATED WAVEFORM:
RESULT:
VIVA QUESTIONS:
1. Write the dataflow model for the IC 74x85.
2. Write the structural program for IC 74x85.
3. How many 4-bit comparators are needed to construct 12-bit comparator?
4. What does a digital comparator mean?
5. Design a 2-bit comparator using gates?
EXPT NO: 6 DATE:
D Flip-Flop 74X74
AIM: To verify and simulate the truth table of D-FlipFlop using VHDL.
APPARATUS REQUIRED:
THEORY:
This device contains two independent positive edge-triggered D flipflops with complementary
outputs. The information on the D input is accepted by the flip-flops on the positive going edge of
the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition
time of the rising edge of the clock.
The data on the D may be changed while the clock is low or high without affecting the outputs as
long as the data setup and hold times are not violated. A LOW logic level on the preset or clear
inputs will set or reset the outputs regardless of the logic levels on the other inputs.
PIN DESCRIPTION OF 74X74 & TRUTH TABLE:
PROGRAM:
library IEEE;
entity dff is
port (
pr_l: in STD_LOGIC; -- active low preset input
clr_l:in STD_LOGIC; -- active low clear input
clk :in STD_LOGIC; -- clock input
d :in STD_LOGIC; -- D input
q :inout STD_LOGIC; -- output of D flip flop
qn :inout STD_LOGIC); -- inverted output
end dff;
architecture dff of dff is

signal e,f,g,h:std_logic;
component nand3
port (
a,b,c: in STD_LOGIC;
d : out STD_LOGIC
);
end component;
begin
g1:nand3 port map(pr_l,h,f,e); -- creates g1 gate
g2:nand3 port map(clr_l,e,clk,f); -- creates g2 gate
g3:nand3 port map(f,clk,h,g); -- creates g3 gate
g4:nand3 port map(g,clr_l,d,h); -- creates g4 gate
g5:nand3 port map(pr_l,f,qn,q); -- creates g5 gate
g6:nand3 port map(q,g,clr_l,qn); -- creates g6 gate
end dff;
--VHDL code for 3 i/p nand gate

library IEEE;
entity nand3 is
port (
a,b,c: in STD_LOGIC;
d : out STD_LOGIC
);
end nand3;
architecture nand3 of nand3 is

begin
d<= not (a and b and c); -- creates a 3 i/p nand gate
end nand3;
PROCEDURE:

Device: XCES100E
Package: VQ100
Speed: -5
box.
your VHDL source.
PRECAUTIONS:
SIMULATED WAVEFORM:
RESULT:
VIVA QUESTIONS:
1. What is the difference between sequential and combinational circuit?
2. What is a flip-flop?
3. Explain the functions of preset and clear inputs in flip-flop.
4. What is meant by a clocked flip-flop?
5. What is meant by excitation table?
6. What is the difference between flip-flop and latch?
EXPT NO: 7 DATE:
JK Flip-Flop 74X109.
AIM: To verify and simulate the operation of JK –FlipFlop using VHDL.
APPARATUS REQUIRED:
THEORY:
The name JK flip-flop is termed from the inventor Jack Kilby from texas instruments. Due to its
versatility they are available as IC packages. The J (Jack) and K (Kilby) are the input states for the
JK flip-flop. The Q and Q’ represents the output states of the flip-flop. According to the table, based
on the inputs, the output changes its state. But, the important thing to consider is all these can occur
only in the presence of the clock signal. The major applications of JK flip-flop are Shift registers,
storage registers, counters and control circuits. Inspite of the simple wiring of D type flip-flop, JK
flip-flop has a toggling nature. This has been an added advantage. Hence they are mostly used in
counters and PWM generation, etc. Here we are using NAND gates for demonstrating the JK flip
flop.Whenever the clock signal is LOW, the input is never going to affect the output state. The clock
has to be high for the inputs to get active. Thus, JK flip-flop is a controlled Bi-stable latch where the
clock signal is the control signal.
The basic NAND gate RS flip-flop suffers from two main problems. Firstly, the condition when S =
0 and R = 0 should be avoided. Secondly, if the state of S or R changes its state while the input
which is enabled is high, the correct latching action does not occur. Thus to overcome these two
problems of the RS Flip-Flop, the JK Flip Flop was designed.
The JK Flip Flop is basically a gated RS flip flop with the addition of the clock input circuitry.
When both the inputs S and R are equal to logic “1”, the invalid condition takes place. Thus to
prevent this invalid condition, a clock circuit is introduced. The JK Flip Flop has four possible input
combinations because of the addition of the clocked input. The four inputs are “logic 1”, ‘logic 0”.
“No change’ and “Toggle”.The basic NAND gate RS flip-flop suffers from two main problems.
Firstly, the condition when S = 0 and R = 0 should be avoided. Secondly, if the state of S or R
changes its state while the input which is enabled is high, the correct latching action does not occur.
Thus to overcome these two problems of the RS Flip-Flop, the JK Flip Flop was designed.
The JK Flip Flop is basically a gated RS flip flop with the addition of the clock input circuitry.
When both the inputs S and R are equal to logic “1”, the invalid condition takes place. Thus to
prevent this invalid condition, a clock circuit is introduced. The JK Flip Flop has four possible input
combinations because of the addition of the clocked input. The four inputs are “logic 1”, ‘logic 0”.
“No change’ and “Toggle”.
LOGIC DIAGRAM:
TRUTH TABLE:
PROGRAM:
Library ieee;
use ieee.std_logic_1164.all; entity jkff1 is
port (PRE,CLK,J,K,CLK:in bit;Q:inout bit;Qn:out bit:='1');
end jkff1;
architecture jkff of jkff1 is

begin
process(PRE,CLR,CLK)
begin
if PRE='0' then Q<='0' after 10ns;
elsif CLR='0' then CLK<='1' after 10ns;
elsif CLK='0' and CLK' event then
J<=(J and not Q) or (not K and Q) after 10ns;
end if;
end process;
Qn<=not Q;
end jkff;
PROCEDURE:

Device: XCES100E
Package: VQ100
Speed: -5
box.
your VHDL source.
PRECAUTIONS:
SIMULATED WAVEFORM:
RESULT:
VIVA QUESTIONS:
1. Why Race around condition occur in JK flip flop?
2. How to overcome race around condition?
3. What are the applications of JK flip flop?
4. What is the difference between RS and JK flip flop?
EX PT NO: 8 DATE:
DECADE COUNTER 74x90
AIM: To verify and simulate the operation of decade counter using VHDL.
APPARATUS REQUIRED:
THEORY:
A Counter is a register capable of counting number of clock pulse arriving at its clock input.
Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of
progressing in increasing order or decreasing order through a certain sequence. An up/down counter
is also called bi-directional counter.
Usually up/down operation of the counter is controlled by up/down signal. When this signal high
counter goes through up sequence and when up/down signal is low counter follows reverse
sequence. The counter counts upwards when UP control are logic ‘1’ and DOWN control is logic
‘0’. In this case the clock input of each flip-flop other than the LSB flip-flop is fed from the normal
output of the immediately preceding flip-flop.
The counter counts downwards when the UP controls input are logic ‘0’ and DOWN control is logic
‘1’. In this case, the clock input of each flip-flop other than the LSB flip-flop is fed from the
complemented output of the immediately preceding flip-flop.
LOGIC DIAGRAM:
PIN DESCRIPTION OF 74X90:
TRUTH TABLE:
OUTPUT
Q(0) Q(3) Q(2) Q(1)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
PROGRAM:
library ieee;
use ieee.std_logic_unsigned.all;
entity decade_CNTR is
port(MR1,MR2,MS1,MS2,clk:in std_logic;
q:out std_logic_vector(3 downto 0));
end decade_CNTR;
architecture beh of decade_CNTR is
begin
process(clk,MR1,MR2,MS1,MS2)
variable x:std_logic_vector(3 downto 0):="0000";
begin
if MR1='1' AND MR2='1'THEN
elsif(MS1='1' and MS2='1') then x:="1001";
elsif (clk'event and clk='1') then
if x<"1001" then x:=x+ 1;
else x:="0000";
end if;
end if;
q<=x;
end process;
end beh;
PROCEDURE:

Device: XCES100E
Package: VQ100
Speed: -5
box.
your VHDL source.
PRECAUTIONS:
SIMULATED WAVEFORM:
RESULT:
VIVA QUESTIONS:
1. What is a sequential circuit?
2. Differentiate between synchronous and asynchronous counter?
3. How many no. of flip-flops are required for decade counter?
4. What is meant by excitation table?
5. Write the difference between signal and variable?
6. If the modulus of a counter is 12 how many flip-flops are required?
EX PT NO: 9 DATE:
UNIVERSAL SHIFT REGISTER -74X194.
AIM: To verify and simulate the operation of universal shift register using VHDL.
APPARATUS REQUIRED:
THEORY:
The 74X194 is a high speed CMOS 4-BIT PIPO SHIFT REGISTER. This SHIFT REGISTER is
designed to incorporate virtually all of the features a system designer may want in a shift register. It
features parallel inputs, parallel outputs, right shift and left shift serial inputs, clear line. The register
has four distinct modes of operation: PARALLEL (broadside) LOAD; SHIFT RIGHT (in the
direction QA QD); SHIFT LEFT; INHIBIT CLOCK (do nothing).
Synchronous parallel loading is accomplished by applying the four data bits and taking both mode
control inputs,S0 and S1 high. The data are loaded into their respective flip-flops and appear at the
outputs after the positive transition of the CLOCK input. During loading, serial data flow is
inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0
is high and S1 is low. Serial data for this mode is entered at the SHIFT RIGHT data input.
When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the SHIFT
LEFT serial input. Clocking of the flip-flops is inhibited when both mode control inputs are low.
The mode control inputs should be changed only when the CLOCK input is high. All inputs are
equipped with protection circuits against static discharge and transient excess voltage.
CONNECTION DIAGRAM:
LOGIC DIAGRAM:
TRUTH TABLE:
PROGRAM:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity usr74194 is Port ( clk, clr_l, lin, rin : in STD_LOGIC;

s : in STD_LOGIC_VECTOR (1 downto 0);
d : in STD_LOGIC_VECTOR (3 downto 0);
q : inout STD_LOGIC_VECTOR (3 downto 0));
end usr74194;
architecture Behavioral of usr74194 is
begin
process (clk, clr_l, lin, rin, s, d, q )
begin
if clr_l = '0' then q<= "0000";
elsif ( clk'event and clk = '1') then
case s is when "00" => q <= q;
when "01" => q <= rin & q (3 downto 1);
when "10" => q <= q (2 downto 0) & lin;
when "11" => q <= d;
when others => q <= "UUUU";
end case;
end if;
end process;
end Behavioral;
PROCEDURE:

Device: XCES100E
Package: VQ100
Speed: -5
box.
your VHDL source.
PRECAUTIONS:
SIMULATED WAVEFORM:
DISCUSSIONS:
RESULT:
VIVA QUESTIONS:
1. What is mean by shift register?
2. What is mean by register?
3. What are the different types of shift registers?
4. Where particularly shift registers are used?

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DIGITAL IC APPLICATIONS LAB

 Xilinx ISE Design Suite 14.7 Software

SIETK, ECE Page |1

SIETK, ECE Page |2

SIETK, ECE Page |3

2-INPUT NAND GATE:

ARCHITECTURE dataflow OF NAND_gate IS

2-INPUT NOR GATE:

SIETK, ECE Page |4

ARCHITECTURE dataflow OF NOR_gate IS

2-INPUT AND GATE:

ARCHITECTURE dataflow OF and_gate IS

architecture Behavioral of orgate is

2-INPUT EX-OR GATE:

ARCHITECTURE dataflow OF exor_gateIS

2-INPUT EX-NOR GATE:

ARCHITECTURE dataflow OF exnor_gate IS

ARCHITECTURE dataflow OF not_gate IS

Fill in the properties in the table as shown below:

SIETK, ECE Page |7

SIETK, ECE Page |8

Half subtractor: The Half-Subtractor is a combinational circuit which is used to perform

SIETK, ECE Page |9

FULL ADDER USING TWO HALF ADDERS:

Logic Diagram Functional Table

Logic Diagram Functional Table

RIPPLE CARRY ADDER:

ARCHITECTURE dataflow OF halfadder IS

ARCHITECTURE dataflow OF halfsubtractor IS

ARCHITECTURE dataflow OF fulladder IS

ARCHITECTURE dataflow OF fullsubtractor IS

RIPPLE CARRY ADDER:

architecture struct_RCA of RCA is

Fill in the properties in the table as shown below:

Device Family: Spartan3E

1. Create project with appropriate file name (preferably lowercase).

EXPT NO: 3 DATE:

ARCHITECTURE DECODER_DFT OF DECODER IS

Fill in the properties in the table as shown below:

Device Family: Spartan3E

8 X 1 MULTIPLEXER -74X151 & 1X4 DEMULTIPLEXER-74X155

8x1 MULTIPLEXER 74151

2X4 DEMULTIPLEXER 74155:

2X4 DEMULTIPLEXER 74155

ARCHITECTURE behavioral OF demux IS

Fill in the properties in the table as shown below:

Device Family: Spartan3E

2X4 DEMULTIPLEXER 74155

(A>B) = A1B1′ +X1A0B0′

architecture comp of comp is

Fill in the properties in the table as shown below:

Device Family: Spartan3E

PIN DESCRIPTION OF 74X74 & TRUTH TABLE:

architecture dff of dff is

--VHDL code for 3 i/p nand gate

architecture nand3 of nand3 is

Fill in the properties in the table as shown below:

Device Family: Spartan3E

AIM: To verify and simulate the operation of JK –FlipFlop using VHDL.

architecture jkff of jkff1 is

Fill in the properties in the table as shown below:

Device Family: Spartan3E

PIN DESCRIPTION OF 74X90:

Fill in the properties in the table as shown below: