Ex.

No: 1 VERIFY THE FUNCTIONALITY OF DIGITAL LOGIC

Date: CIRCUITS USING TEST BENCH

OBJECTIVE:
 To write test bench code for digital logic circuits using verilog HDL
AIM:
 To implement and verify the function of digital logic circuits using test bench code
in FPGA kit.
 To generate synthesis report by using scripting language

EXAMPLES OF CIRCUITS FOR TEST BENCH CODING:

 Students can select any one of the examples of circuits given below or bring
their own circuit for test bench coding
S.No Examples of circuit for test bench coding
1. Half adder
2. Multiplexer
3. D-flip flop

SOFTWARE AND HARDWARE REQUIRED:

 Xilinx ISE
 FPGA-Spartan 6

THEORY:
VLSI stands for Very Large Scale Integration. The use of CMOS technology results
in low power consumption and area reduction. The circuits can be designed in both ways
either using the HDL language or by schematic entry method. HDL stands for Hardware
Description Language. There are two types of HDL language such as Very High Speed
Integrated Circuits Hardware Description Language (VHDL) and Verilog HDL.VLSI deals
with the digital circuits. Both front-end and backend tools are available in VLSI. Front end
is used for simulation purpose. Back end tool is used for power and area analysis. For
example Xilinx ISE and Modelsim are the two front end tools. Simulator is used to check
the program is correct or not. Xilinx ISE is used for implementation. ISE stands for
Integrated Software Environment.

VLSI physical design steps involve floor planning, placement and routing. The cell
location is predetermined in floor planning. Placement is placing the cells in the position
according to floor planning. Routing is done between the cells for the connection.

Logic circuits are an electronic circuit which makes logical decisions. Each gate has
one or more input and only one output. The most common logic gates used are OR, AND
and NOT gates. The NAND, NOR gates are called as the Universal gates because both can
be used to implement any gate like AND, OR, and NOT gates or combination of these
basic gates. Both the combinational and sequential digital circuits can be implemented in
VLSI. Combinational circuits depend only in the present input. Sequential circuits depend
both on the present input and past output.
Internals of each module can be defined at four levels of abstraction, depending on
the needs of the design.
Behavioral or algorithmic level:
 This is the highest level of abstraction provided by Verilog HDL. A module can be
implemented in terms of the desired design algorithm without concern for the
hardware implementation details. Designing at this level is very similar to C
programming.
Dataflow level:

 At this level, the module is designed by specifying the data flow. The designer is
aware of how data flows between hardware registers and how the data is processed in
the design.
Gate level:

 The module is implemented in terms of logic gates and interconnections between these
gates. Design at this level is similar to describing a design in terms of a gate-level
logic diagram.
Switch level:

 This is the lowest level of abstraction provided by Verilog. A

module can be implemented in terms of switches, storage nodes, and the
 interconnections between them. Design at this level requires knowledge of switch-
level implementation details. Verilog allows the designer to mix and match all
four levels of abstractions in a design.

Testbench:

It checks whether the RTL Implementation meets the design spec or not.

1. HALF ADDER

The half adder is a combinational logic circuit with two inputs and two outputs. The
half adder circuit is designed to add two single bit binary number A and B shown in below
figure. It is the basic building block for addition of two single bit numbers. This circuit has
two outputs carry (c) and sum (s). Truth table of half adder is shown in table.

Figure : Block diagram of half adder

Logic Diagram:
Table : Truth table for half adder

Input Output
a b s c
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Figure : Logic diagram for half adder
Program:

TestBench:
output

Structural model Dataflow model Behavioral model

2. MULTIPLEXER
The multiplexer is a special type of combinational circuit. There are n-data inputs,
one output and s-select inputs. It is a digital circuit which selects one of the n data inputs
and routes it to the output. The selection of one of the n inputs is done by the selected
inputs. The block diagram of multiplexer is shown in figure . The truth table of 4:1
multiplexer is shown in table.
 Figure : Block diagram of multiplexer
Logic diagram:

Figure : Logic diagram for 4:1 multiplexer

Table : Truth table for Multiplexer

S0 S1 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Program:

TestBench
output

Structural model Dataflow model Behavioral model

3. D-FLIP-FLOP:

The D flip-flop is also known as a "data" or "delay" flip-flop. The D flip-flop

captures the value of the D-input at a definite portion of the clock cycle (such as the rising
edge of the clock). That captured value becomes the Q output. At other times, the output Q
does not change. The D flip-flop can be viewed as a memory cell, a zero-order hold, or
a delay line.

Figure : Logic diagram for D flip flop

Table : Truth table for D flip flop

Clock (c) d q(next)
1 0 0
1 1 1
0 X No change

D FLIP FLOP:
TestBench

output

Behavioral model Dataflow model Structural model

PROCEDURE:
Step1: Open Xilinx ISE and create a new project.
Step 2: Select the Family, Device, Package and Speed of Xilinx board and also
select your programming language (Verilog/VHDL).
Step 3: Click on Project > New Source
Step 4: Select Source type is Verilog Module and enter the file name
(ANDing_code).
Step 5: Define Module Window.
Step 6: Summery Window
Step 7: The Project Navigator window looks like below window.
Write a program for ANDing operator in module present in project navigator.
Step 8: Click on Project > New Source. Select Implementation Constraints file type
and enter the file name (e.g. pinout).
Step 9: Write the inputs, outputs and its pin location in proper format of .ucf file.
(use datasheet of Xilinx board for pin location). Here two switches SW0 and
SW1 are used for input and one led LD0 is used for output.
Step 10: Open main ANDing program and double click on Synthesize – XST. After
successful completion of Synthesis, double click on Implement
Design. Implement design consists of three parts-
o Translate
o Map
o Place and Route
Step 11: Double click on Configure Target Device and a new ISE
iMPACT window open.
Step 12: Connect the Xilinx board to your PC/Laptop using USB cable.
Step 13: Double click on Boundary scan. Check auto cable connection Output >
 Cable Auto Connect and if cable is connected then Window bottom part
looks like step 3 shown in below.
Step 14: Click on File > Initialize Chain. After that they ask for “Do you want to
continue and assign configuration files(s)?”
Step 15: Click on Open. After that they ask “Do you want to attach an SPI or BPI
PROM to this device?” click on No tab. Click on Operations >
Program. If Programming successful then they shows Program
Succeeded.
Step 16: Check the output on hardware (Board). Here I am giving input through
switches and output shows on LED. Output:
o Switch1(OFF) AND Switch2(OFF) = LED(OFF)
o Switch1(ON) AND Switch2(OFF) = LED(OFF)
o Switch1(OFF) AND Switch2(ON) = LED(OFF)
o Switch1(ON) AND Switch2(ON) = LED(ON)

OUTPUT:

HALF ADDER
MULTIPLEXER

D FLIP FLOP

PRE LAB QUESTIONS:

1. What do you mean by HDL in VLSI?
2. What are arithmetic circuits in VLSI design?
3. Compare combinational circuit and sequential circuit.
4. How many NAND gates are required to construct a half adder?
5. What is test bench?

POST LAB QUESTIONS:

1. An AND gate and OR gate are given inputs don’t care (X) & 1 , what is expected
output
2. How do you convert XOR gate into a buffer & an inverter (use only one XOR gate for
each)
3. Design a 2:1 mux using half adders
4. Write a program of half subtractor using gate level in Verilog HDL.
5. What is the difference between high impedance state of the signal(Z) and unknown
state of the signal (X)
RESULT:

CORE-COMPETENCY LEARNED:

MARKS ALLOCATION

Marks Marks
Details
Allotted Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 10
Basic understanding (Core competency learned) 15
Viva 10
Record 10
 Total 100

Repetition: less 25% of the total marks awarded as above.

Signature of faculty

Ex. No: 2 APPLICATION CIRCUIT MODEL BY FINITE STATE

Date: MACHINE (FSM)

OBJECTIVE:
 To write Verilog code for application circuits by FSM
AIM:
 To design FSM for various application circuit using Verilog HDL and implement in
FPGA.
 To generate synthesis report by using scripting language
EXAMPLES OF CIRCUITS FOR APPLICATION CIRCUIT:
 Students can select any one of the FSM given below or bring their own FSM for
application circuit
S.No Examples of FSM for application circuit
1. Gray code counter
2. Sequence detector (1011- overlapping
sequence)
3. Electronic combination lock
SOFTWARE AND HARDWARE REQUIRED:
 Xilinx ISE
 FPGA-Spartan 6

THEORY:
State machine types:
There are two principle state machine classifications that apply to all state machine designs.
Moore -vs- Mealy:
A Moore State machine is classified as an FSM where the outputs are only a function of the
present state, while Mealy state machines have one or more outputs that are a function of the
present state and one or more FSM inputs.

Figure - Moore & Mealy State Machine block diagram

EXAMPLE OF FSM DESIGN:

1. GRAY CODE COUNTER (3-bit)
It will have following sequence of states. It can be implemented without FSM also.

000
001
011
010
110
111
101
100

Program

2. SEQUENCE DETECTOR:
Let us design a circuit to detect a sequence of 1011 in serial input. This is an overlapping
sequence. So, if 1011011 comes, sequence is repeated twice. Consider these two circuits.
First one is Moore and second one is Mealy. In Moore design below, output goes high only
if state is 100. Note that we have used 1 less state than Mealy and hence one flip flop less
will be enough to design state machine.
When reset, state goes to 00, where there is no previous inputs. State remains same until we
get a '1' in the input since there is no possibility of start of sequence. If a 1 comes in the
input, it may be start of sequence, so go to state 01. From 01, if again 1 comes, that means
sequence is broken. But there is a possibility of start of another new sequence. So, 01 is start
of sequence and stay in the same state. If zero comes, go to state 10.

Another 0 when state is 10 breaks the sequence and state goes to 00, no sequence. If 1
comes, continue to next state 11.

If again 1 comes, sequence completes. Make the output high and go to state 01, because
there may be a overlapping sequence. If zero comes, sequence breaks and state goes to 10
since it may be second bit of another sequence.

Program:
3. ELECTRONIC COMBINATION LOCK SYSTEM:
In this lock system, only two digits are used to unlock system. With the help of "0" and "1",
the lock will be unlock but with specific pattern. This lock will be unlock with "01011" code.
If this pattern will be identified by lock then lock will be become open and output unlock bit
will be "1", otherwise lock remain close and unlock bit will be "0". This Lock System is
developed using FSM and there are total six stages.

State diagram:
Program:
PROCEDURE:
Step1: Open Xilinx ISE and create a new project.
Step 2: Select the Family, Device, Package and Speed of Xilinx board and also
select your programming language (Verilog/VHDL).
Step 3: Click on Project > New Source
Step 4: Select Source type is Verilog Module and enter the file name
(ANDing_code).
Step 5: Define Module Window.
Step 6: Summery Window
Step 7: The Project Navigator window looks like below window.
Write a program for ANDing operator in module present in project navigator.
Step 8: Click on Project > New Source. Select Implementation Constraints file type
and enter the file name (e.g. pinout).
Step 9: Write the inputs, outputs and its pin location in proper format of .ucf file.
(use datasheet of Xilinx board for pin location). Here two switches SW0 and
SW1 are used for input and one led LD0 is used for output.
Step 10: Open main ANDing program and double click on Synthesize – XST. After
successful completion of Synthesis, double click on Implement
Design. Implement design consists of three parts-
o Translate
o Map
o Place and Route
Step 11: Double click on Configure Target Device and a new ISE
iMPACT window open.
Step 12: Connect the Xilinx board to your PC/Laptop using USB cable.
Step 13: Double click on Boundary scan. Check auto cable connection Output >
Cable Auto Connect and if cable is connected then Window bottom part
looks like step 3 shown in below.
Step 14: Click on File > Initialize Chain. After that they ask for “Do you want to
continue and assign configuration files(s)?”
Step 15: Click on Open. After that they ask “Do you want to attach an SPI or BPI
PROM to this device?” click on No tab. Click on Operations >
 Program. If Programming successful then they shows Program
Succeeded.
Step 16: Check the output on hardware (Board). Here I am giving input through
switches and output shows on LED. Output:
o Switch1(OFF) AND Switch2(OFF) = LED(OFF)
o Switch1(ON) AND Switch2(OFF) = LED(OFF)
o Switch1(OFF) AND Switch2(ON) = LED(OFF)
o Switch1(ON) AND Switch2(ON) = LED(ON)

PRE LAB QUESTIONS:

1. What is the definition of Moore machine?
2. Compare Melay and Moore model.
3. What are the three conditions that give rise to output glitches?
4. Give the application of FSM
POST LAB QUESTIONS:
1. How to write FSM is verilog?
2. Design binary divisibility by 2 using Verilog HDL.
3. Design a circuit that detects three consecutive '1's using Mealy and Moore FSM

RESULT:
CORE-COMPETENCY LEARNED:

MARKS ALLOCATION

Marks Marks
Details
Allotted Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 10
Basic understanding (Core competency learned) 15
Viva 10
Record 10
Total 100

Repetition: less 25% of the total marks awarded as above.

Signature of faculty
Ex. No: 3 DC AND TRANSIENT CHARACTERISTICS OF STATIC AND
Date: DYNAMIC CMOS CIRCUITS

OBJECTIVES:
 To design static and dynamic CMOS circuits
 To analyse the DC and transient characteristics of CMOS circuits

AIM:
 To model, simulate and verify the logic function of CMOS circuits using SPICE tool
 To analyse the power, area and delay by performing pre layout simulations for
CMOS circuits

EXAMPLES OF CMOS CIRCUITS:

 Students can select any one of the examples of CMOS circuits given below or bring
their own CMOS circuit

S.No Examples of CMOS circuits

1. CMOS inverter
2. CMOS NAND
3. CMOS D-latch

SOFTWARE REQUIRED:
 Tanner EDA tool

THEORY:
Static circuits:
 Static CMOS circuits with complementary nMOS pull-down and pMOS pull-up
networks are used for the vast majority of logic gates in integrated circuits. Its have
good noise margins, and are fast, low power, insensitive to device variations, easy
 to design, widely supported by CAD tools, and readily available in standard cell
libraries
 When noise does exceed the margins, the gate delay increases because of the glitch,
but the gate eventually will settle to the correct answer. Most design teams now use
static CMOS exclusively for combinational logic
 Nevertheless, performance or area constraints occasionally dictate the need for other
circuit families. The most important alternative is dynamic circuits
Dynamic Circuits:
 Ratioed circuits reduce the input capacitance by replacing the pMOS transistors
connected to the inputs with a single resistive pull-up.
 The drawbacks of ratioed circuits include slow rising transitions, contention on the
falling transitions, static power dissipation, and a nonzero VOL. Dynamic circuits
circumvent these drawbacks by using a clocked pull-up transistor rather than a
pMOS that is always ON.
 Dynamic circuits are the fastest commonly used circuit family because they have
lower input capacitance and no contention during switching
CMOS INVERTER
Diagram:

DC Analysis
SPICE Netlist:

Output

Transient Analysis

SPICE Netlist:

Power Results
Output

CMOS NAND GATE

Diagram:

Program:

CMOS D-LATCH
Diagram:
SPICE Netlist:

Output

PROCEDURE:
1. Open SPICE tool and draw the circuit.
2. Set the circuit analysis in the T-SPICE window.
3. Simulate and verify the functionality of the circuit through the waveform.
4. End the process.

PRE LAB QUESTIONS:

1. What is Tanner EDA tool in VLSI?
2. How will you design CMOS NAND circuit using S-Edit?
3. What is T Spice?
4. List out the steps to design the circuit in Tanner.
POST LAB QUESTIONS:
1. Why do you use Tanner EDA tool? What are the other EDA tools available?
2. What is the difference between backend and front end?
3. What is the importance of AC analysis, DC analysis and transient analysis in the
analog circuit design?
4. What happens when the PMOS and NMOS are interchanged with one another in an
inverter?
RESULT:

CORE-COMPETENCY LEARNED:

MARKS ALLOCATION

Marks Marks
Details
Allotted Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 10
Basic understanding (Core competency learned) 15
Viva 10
Record 10
Total 100

Repetition: less 25% of the total marks awarded as above.

Signature of faculty
Ex. No: 4
LAYOUT DIAGRAM FOR CMOS CIRCUITS
Date:

OBJECTIVE:
 To design layout diagram for various static and dynamic CMOS circuit
AIM:
 To draw the layout of CMOS circuits which selected in ex no.3 and simulate using
SPICE tool
 To analyse the power, area and delay by performing post layout simulations and
compare its value with prelayout simulation value of same CMOS circuits (Ex.
No.:3)

EXAMPLES OF LAYOUT DIAGRAM:

 Students can select any one of the examples of layout diagram of CMOS circuit
given below or bring their own layout diagram of CMOS circuit which selected
in ex no.3

S.No Examples of layout diagram of CMOS circuits

1. CMOS Inverter
2. CMOS NAND gate
3. CMOS D-latch

SOFTWARE REQUIRED:
 Tanner EDA tool or Microwind Tool

THEORY:
 Layout design rules describe how small features can be and how closely they can be
reliably packed in a particular manufacturing process
 Designers often describe a process by its feature size. Feature size refers to minimum
transistor length, so  is half the feature size.
 The rules describe the minimum width to avoid breaks in a line, minimum spacing to
avoid shorts between lines, and minimum overlap to ensure that two layers completely
overlap.
 In VLSI design, as processes become more and more complex, need for the designer
to understand the intricacies of the fabrication process and interpret the relations
between the different photo masks is really troublesome.
 Therefore, a set of layout rules, also called design rules, has been defined. They act
as an interface or communication link between the circuit designer and the process
engineer during the manufacturing phase.
 Types of Design Rules
1. Scalable Design Rules (e.g. SCMOS, λ-based design rules)
2. Absolute Design Rules (e.g. μ-based design rules)
LAYOUT DIAGRAM:

OUTPUT
PROCEDURE:
1. Draw the CMOS Inverter layout by obeying the lambda rules using different layer of
mask
2. Check DRC to verify whether any region violate the lambda rule
3. Verify the function of layout diagram through run option

PRE LAB QUESTIONS:

1. What is the purpose of DRC?
2. What is meant by feature size?
3. List out the various design rules.
4. What are the advantages of Layout design?
POST LAB QUESTIONS:
1. Why is the layout diagram needed in VLSI?
2. How does the layout design differ from schematic design?
3. Create the layout for the CMOS NOR gate
4. What is meant by post-layout simulation?
RESULT:

CORE-COMPETENCY LEARNED:

MARKS ALLOCATION

Marks Marks
Details
Allotted Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 10
Basic understanding (Core competency learned) 15
Viva 10
Record 10
Total 100

Repetition: less 25% of the total marks awarded as above.

Signature of faculty
Ex. No: 5
DIGITAL CIRCUIT LOGIC USING SYSTEM VERILOG (SV)
Date:

OBJECTIVE:
 To design digital logic circuits using SystemVerilog hardware description language.
AIM:
 To write code for digital circuit using SystemVerilog
 To simulate and verify the function of digital logic circuit using EDA tool

EXAMPLES OF CIRCUITS FOR CODING:

 Students can select any one of the examples of circuit given below or bring their
own circuit for coding

S.No Example circuits

1. Logic gates and D-flipflop
2. 4x1 multiplexer and counter

SOFTWARE REQUIRED:
 Modelsim or Vivado
THEORY:
Hardware description language like Verilog and VHDL are used to describe
hardware behavior so that it can be converted to digital blocks made up of combinational
gates and sequential elements. In order to verify that the hardware description in HDL is
correct, there is a need for a language with more features in OOP that will support
complicated testing procedures and is often called a hardware Verification Language.
SystemVerilog is an extension of Verilog with many such verification features that
allow engineers to verify the design using complex testbench structures and random stimuli
in simulation
PROGRAM:
Logic gates:

4x1 Multiplexer:

D-flip-flop:

Counter:
PROCEDURE:
 The modelsim is opened. In the file menu new project is selected.
 In new project wizard name is mentioned then in new project wizard device
properties simulator is selected and finish is chosen.
 In project, new source-select type, verilog module is chosen and file name is given
then the program for digital circuits have been designed and saved.
 Syntax is verified by using the check syntax option in process navigator bar.
 Simulation is done by selecting behavioral simulation from source window and the
corresponding file is selected.
 Then simulator is chosen and the simulated output waveform will
be generated.
PRE-LAB QUESTIONS:
1. What is the role of verification engineer in IC design? Compare UVM, OVM, VMM
and AVM.
2. What is the difference between logic[7:0] and byte variable in SystemVerilog?
3. What is the difference between a bit and logic data type?
4. What is the difference between a reg, wire and logic in SystemVerilog?
5. What is the difference between “forever” and “for” in SystemVerilog ?

POST-LAB QUESTIONS:
1. Sketch a schematic of the circuit described by the following HDL code.
module exercise1(input logic a, b, c,
output logic y, z);
assign y = a & b & c | a & b & ~c | a & ~b & c;
assign z = a & b | ~a & ~b;
endmodule
2. Write an HDL module that computes a 4-input XOR function. The input is A3:0 and the
output is Y.
3. Write a self-checking testbench for above question no. 2.
4. Explain the difference between blocking and nonblocking assignments in
SystemVerilog. Give examples.
RESULT:

CORE-COMPETENCY LEARNED:

MARKS ALLOCATION

Marks Marks
Details
Allotted Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 10
Basic understanding (Core competency learned) 15
Viva 10
Record 10
Total 100

Repetition: less 25% of the total marks awarded as above.

 Signature of faculty

Ex. No: 6 ADDER AND MULTIPLIER LOGIC USING ARITHMETIC

Date: BUILDING BLOCKS BY VERILOG HDL

OBJECTIVE:
 To design adder and multiplier logic using arithmetic building blocks.
AIM:
 To write Verilog code for adder and multiplier logic using arithmetic building blocks
 To simulate and verify the function of digital logic circuit using EDA tool

EXAMPLES OF CIRCUITS FOR DESIGN:

 Students can select any one of the examples of circuit given below or bring their
own circuit for design

S.No Example circuits

1. Ripple carry adder(RCA)
2. Simple unsigned combinational multiplier
3. 4 bit Wallace tree multiplier

SOFTWARE REQUIRED:
 Xilinx ISE
THEORY:
Chip functions generally can be divided into the following categories:
 Datapath operators
 Memory elements
 Control structures
 Special-purpose cells
 I/O
 Power distribution
 Clock generation and distribution
 Analog and RF
 Addition forms the basis for many processing operations, from ALUs to address
generation to multiplication to filtering. As a result, adder circuits that add two binary
numbers are of great interest to digital system designers. An extensive, almost endless,
assortment of adder architectures serve different speed/power/area requirements.
Multiplication is less common than addition, but is still essential for microprocessors,
digital signal processors, and graphics engines. The most basic form of multiplication
consists of forming the product of two unsigned (positive) binary numbers. There are a
number of techniques that can be used to perform multiplication. In general, the choice is
based upon factors such as latency, throughput, energy, area, and design complexity.
More efficient parallel approaches use some sort of array or tree of full adders to
sum the partial products. We begin with a simple array for unsigned multipliers, and then
modify the array to handle signed two’s complement numbers using the Baugh-Wooley
algorithm. The number of partial products to sum can be reduced using Booth encoding and
the number of logic levels required to perform the summation can be reduced with Wallace
trees.
1. RIPPLE CARRY ADDER(RCA):

N-bit full adder can be designed by cascading N number of 1-bit full adders. Each
full adder takes a carry-in (C0), which is the carry-out (C4) of the previous adder. This kind
of chain of adders forms a ripple-carry adder, since each carry-bit "ripples" to the next full
adder. The layout of a ripple-carry adder is simple, which allows for fast design time;
however, the ripple-carry adder is relatively slow, since each full adder must wait for the
carry-bit to be calculated from the previous full adder. A 4-bit ripple carry adder formed by
cascading four 1-bit full adders is shown in Figure.
 Fig: Ripple Carry Adder (4-bit) Block Diagram
Program (Ripple Carry Adder(RCA))

module full_adder(
input a, b, c_in,
output s, c_out);

wire net1, net2, net3;

xor (net1, a, b);

xor (s, net1, c_in);
and (net2, net1, c_in);
and (net3, a, b);
or (c_out, net2, net3);

endmodule

module full_adder4(
input [3:0] a, b,
input c_in,
output [3:0] s,
output c_out);

`ifdef NO_GATES
wire [4:0] sum;
assign sum = a + b + c_in;
assign s = sum[3:0];
assign c_out = sum[4];

`else
wire [2:0] carry;

full_adder fa0(
.a(a[0]),
.b(b[0]),
.c_in(c_in),
.s(s[0]),
.c_out(carry[0]));
full_adder fa1(
.a(a[1]),
.b(b[1]),
.c_in(carry[0]),
.s(s[1]),
.c_out(carry[1]));
full_adder fa2(
.a(a[2]),
.b(b[2]),
.c_in(carry[1]),
.s(s[2]),
.c_out(carry[2]));
full_adder fa3(
.a(a[3]),
.b(b[3]),
.c_in(carry[2]),
 .s(s[3]),
.c_out(c_out));
`endif

endmodule
Output (Ripple Carry Adder(RCA))

2. SIMPLE UNSIGNED COMBINATIONAL MULTIPLIER:

Mx N-bit multiplication P = Yx X can be viewed as forming N partial products of M
bits each, and then summing the appropriately shifted partial products to produce an M+ N-
bit result P. Binary multiplication is equivalent to a logical AND operation. Therefore,
generating partial products consists of the logical ANDing of the appropriate bits of the
multiplier and multiplicand.
Each column of partial products must then be added and, if necessary, any carry values
passed to the next column.Figure illustrates the generation, shifting, and summing of partial
products in a 6 × 6-bit multiplier.
Program (Simple Unsigned Combinational Multiplier)
module jhalfadder(sum,carry,a,b);
output sum,carry;
input a,b;

assign sum = a^b;

assign carry = a&b;

endmodule

module jfulladder(y,carryout,a,b,carryin);
output y,carryout;
input a,b,carryin;

assign y = a ^ b ^ carryin;
assign carryout = ( a & b ) | ( a & carryin ) | ( b & carryin );

endmodule
module junsignedArrayMultiplier(PRODUCT, A, B);
output [7:0] PRODUCT;
input [3:0] A, B;

wire [14:0] W;
wire [10:0] C;
wire [5:0] S;

and and00 ( W[0], A[0], B[1] );

and and01 ( W[1], A[0], B[2] );
and and02 ( W[2], A[0], B[3] );

and and03 ( W[3], A[1], B[0] );

and and04 ( W[4], A[1], B[1] );
and and05 ( W[5], A[1], B[2] );
and and06 ( W[6], A[1], B[3] );

and and07 ( W[7], A[2], B[0] );

and and08 ( W[8], A[2], B[1] );
and and09 ( W[9], A[2], B[2] );
and and10 ( W[10], A[2], B[3] );

and and11 ( W[11], A[3], B[0] );

and and12 ( W[12], A[3], B[1] );
and and13 ( W[13], A[3], B[2] );
and and14 ( W[14], A[3], B[3] );
 and and15 ( PRODUCT[0], A[0], B[0] );

jhalfadder jha01 ( PRODUCT[1], C[0], W[0], W[3] );

jfulladder jfa01 ( S[0], C[1], W[1], W[4], C[0] );
jfulladder jfa02 ( S[1], C[2], W[2], W[5], C[1] );
jhalfadder jha02 ( S[2], C[3], W[6], C[2] );
jhalfadder jha03 ( PRODUCT[2], C[4], W[7], S[0] );
jfulladder jfa03 ( S[3], C[5], W[8], S[1], C[4] );
jfulladder jfa04 ( S[4], C[6], W[9], S[2], C[5] );
jfulladder jfa05 ( S[5], C[7], W[10], C[3], C[6] );
jhalfadder jha04 ( PRODUCT[3], C[8], W[11], S[3] );
jfulladder jfa06 ( PRODUCT[4], C[9], W[12], S[4], C[8] );
jfulladder jfa07 ( PRODUCT[5], C[10], W[13], S[5], C[9] );
jfulladder jfa08 ( PRODUCT[6], PRODUCT[7], W[14], C[7], C[10] );
endmodule
Output (Simple Unsigned Combinational
Multiplier)
3. 4-BIT WALLACE TREE MULTIPLIER
The main aim of our research area first to describe the Functionality of the desired
wallace tree using Verilog HDL. The multiplier takes in two 4-bit operands: the multiplier
(MR) and the multiplicand (MD), and produces the 8-bit multiplication result of the two at
its output . The Desired architecture of the multiplier primarily consists of four major
modules. They are: 2's Complement Generator, Partial Product Generator, Wallace Tree and
Carry Look-ahead Adder. The multiplier has been constructed in its simplest conceptual
form. The 2's Complement Generator uses a Ripple Carry Adder constructed from Full-
adder modules. The Partial Product Generator uses MD or –MD and MR or –MR for
creating 4 partial products of 8 bit. The 4partial products are supplied to Wallace Tree and
added appropriately.

The Wallace tree uses both Full Adder and Half Adders. The final 8-bit intermediate results
are added using a Carry Look-ahead Adder.

Function and Algorithm of the Modules:

a) 2's Complement Generator: Function: The 2's Complement Generator Takes the
multiplicand MD and MR as its input and produces –MD and - MR as its output in case of
negative numbers. Algorithm: 2's complement is generated by inverting all bits of the
multiplicand and then adding 1 using a ripple carry adder.

b) Partial Product Generator: Function: The Partial Product Generator generates

appropriate partial products to be added with a Wallace tree. Algorithm: The Partial Product
Generator uses the table for each multiplier bit. Depending on the value of MD or -MD or
MR or-MR is assigned to partial product. 4 bit is then extended till the 7th bit for
appropriate sign extension.

c) Wallace Tree: Function: The Wallace tree module adds the 4 partial products and
generates final two intermediate operands for final addition

d) Carry Look-ahead Adder: Function: Carry Look-ahead Adder (CLA) add two numbers
with very lower latency. Algorithm: By extend the cin with the corresponding inputs, the
carry and sum are independent of the previous bits
PROGRAM (4 Bit Wallace tree multiplier)
module wallace(A,B,prod);
input [3:0] A,B;
output [7:0] prod;
Wire
s11,s12,s13,s14,s15,s22,s23,s24,s25,s26,s32,s33,s34,s35,s36,s37;
wire
c11,c12,c13,c14,c15,c22,c23,c24,c25,c26,c32,c33,c34,c35,c36,c37;
wire [6:0] p0,p1,p2,p3;

assign p0 = A & {4{B[0]}};

assign p1 = A & {4{B[1]}};
assign p2 = A & {4{B[2]}};
assign p3 = A & {4{B[3]}};
assign prod[0] = p0[0];
assign prod[1] = s11;
assign prod[2] = s22;
assign prod[3] = s32;
assign prod[4] = s34;
assign prod[5] = s35;
assign prod[6] = s36;
assign prod[7] = s37;

half_adder ha11 (p0[1],p1[0],s11,c11);

full_adder fa12(p0[2],p1[1],p2[0],s12,c12);
full_adder fa13(p0[3],p1[2],p2[1],s13,c13);
full_adder fa14(p1[3],p2[2],p3[1],s14,c14);
half_adder ha15(p2[3],p3[2],s15,c15);
half_adder ha22 (c11,s12,s22,c22);
full_adder fa23 (p3[0],c12,s13,s23,c23);
full_adder fa24 (c13,c32,s14,s24,c24);
full_adder fa25 (c14,c24,s15,s25,c25);
full_adder fa26 (c15,c25,p3[3],s26,c26);
 half_adder ha32(c22,s23,s32,c32);
half_adder ha34(c23,s24,s34,c34);
half_adder ha35(c34,s25,s35,c35);
half_adder ha36(c35,s26,s36,c36);
half_adder ha37(c36,c26,s37,c37);

endmodule

OUTPUT-4 bit Wallace tree multiplier:

PROCEDURE:
 The Xilinx ISE 12.4 is opened. In the file menu new project is selected.
 In new project wizard name is mentioned then in new project wizard device
properties ISE simulator is selected and finish is chosen.
 In project, new source-select type, verilog module is chosen and file name is given
then the program for digital circuits have been designed and saved.
 Syntax is verified by using the check syntax option in process navigator bar.
 Simulation is done by selecting behavioral simulation from source window and the
corresponding file is selected.
 Then Xilinx ISE simulator is chosen and the simulated output
waveform will be generated.
RESULT:
Thus,the Ripple carry adder(RCA),Simple unsigned combinational
multiplier and 4 bit Wallace tree multiplier are performed in the EDA tool
and tested the output with some values and got the output which is expected.

CORE-COMPETENCY LEARNED:
I have understood the concept of carry select adder and also learned how to
construct the program and test bench code for Ripple carry adder(RCA),Simple
unsigned combinational multiplier and 4 bit Wallace tree multiplier , and also
I have understood that how to verify output using EDA tool .

MARKS ALLOCATION

Marks Marks
Details
Allotted Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 10
Basic understanding (Core competency learned) 15
Viva 10
Record 10
Total 100

Repetition: less 25% of the total marks awarded as above.

Signature of faculty
Ex. No: 7 DESIGN A PROTOCOL USING VERILOG/SYSTEM VERILOG
Date: AND VERIFY USING UVM METHODOLOGY

OBJECTIVE:
 To design protocol using system Verilog and verify its concept using UVM
methodology.
AIM:
 To write System Verilog code for APB protocol
 To simulate and verify the function of APB protocol using EDA tool

EXAMPLES OF CIRCUITS FOR DESIGN:

 Students can select APB protocol or bring any protocol for design

SOFTWARE REQUIRED:
 Modelsim

THEORY:
AMBA 3 APB PROTOCOL (Spec.)
 The APB is part of the AMBA 3 protocol family. It provides a low-cost interface that
is optimized for minimal power consumption and reduced interface complexity.
 The APB interfaces to any peripherals that are low-bandwidth and do not require the
high performance of a pipelined bus interface. The APB has unpipelined protocol.
 All signal transitions are only related to the rising edge of the clock to enable the
integration of APB peripherals easily into any design flow. Every transfer takes at
least two cycles.
 The APB can interface with the AMBA Advanced High-performance Bus Lite
(AHB-Lite) and AMBA Advanced Extensible Interface (AXI).
TRANSFERS
It contains the following sections:
 i. Write transfers
ii. Read transfers
iii. Error response.

(i) WRITE TRANSFERS

Two types of write transfer are described in this section:
• With no wait states
• With wait states.
1. With no wait states
Figure shows a basic write transfer with no wait states.

Figure :Write transfer with no wait states

The write transfer starts with the address, write data, write signal and select signal all
changing after the rising edge of the clock. The first clock cycle of the transfer is called the
Setup phase. After the following clock edge the enable signal is asserted, PENABLE, and
this indicates that the Access phase is taking place. The address, data and control signals all
remain valid throughout the Access phase. The transfer completes at the end of this cycle.
The enable signal, PENABLE, is deasserted at the end of the transfer. The select
signal, PSELx, also goes LOW unless the transfer is to be followed immediately by another
transfer to the same peripheral.

2. With wait states

 Figure shows how the PREADY signal from the slave can extend the transfer.
During an Access phase, when PENABLE is HIGH, the transfer can be extended by driving
PREADY LOW. The following signals remain unchanged for the additional cycles:
• address, PADDR
• write signal, PWRITE
• select signal, PSEL
• enable signal, PENABLE
• write data, PWDATA.

Figure : Write transfer with wait states

PREADY can take any value when PENABLE is LOW. This ensures that
peripherals that ave a fixed two cycle access can tie PREADY HIGH.

(ii) READ TRANSFERS

Two types of read transfer are described in this section:
• With no wait states
• With wait states.
1. With no wait states
Figure shows a read transfer. The timing of the address, write, select, and enable
signals are as described in Write transfers. The slave must provide the data before the end of
the read transfer.
 Figure: Read transfer with no wait states
2. With wait states
Figure shows how the PREADY signal can extend the transfer. The transfer is
extended if PREADY is driven LOW during an Access phase. The protocol ensures that the
following remain unchanged for the additional cycles:
• address, PADDR
• write signal, PWRITE
• select signal, PSEL
• enable signal, PENABLE.
Figure shows that two cycles are added using the PREADY signal. However, you can add
any number of additional cycles, from zero upwards.

Figure: Read transfer with wait states

(iii) ERROR RESPONSE

You can use PSLVERR to indicate an error condition on an APB transfer. Error
conditions can occur on both read and write transactions.
PSLVERR is only considered valid during the last cycle of an APB transfer, when
PSEL, PENABLE, and PREADY are all HIGH.
It is recommended, but not mandatory, that you drive PSLVERR LOW when it is
not being sampled. That is, when any of PSEL, PENABLE, or PREADY are LOW.
Transactions that receive an error, might or might not have changed the state of the
peripheral. This is peripheral-specific and either is acceptable.
When a write transaction receives an error this does not mean that the register within
the peripheral has not been updated. Read transactions that receive an error can return
invalid data. There is no requirement for the peripheral to drive the data bus to all 0s for a
read error.
APB peripherals are not required to support the PSLVERR pin. This is true for both
existing and new APB peripheral designs. Where a peripheral does not include this pin then
the appropriate input to the APB bridge is tied LOW.

1. Write transfer
Figure shows an example of a failing write transfer that completes with an error.

Figure: Example failing write transfer

2. Read transfer
A read transfer can also complete with an error response, indicating that there is no
valid read data available. Figure shows a read transfer completing with an error response.

Figure: Example failing read transfer

3. Mapping of PSLVERR
When bridging:
 From AXI to APB An APB error is mapped back to RRESP/BRESP =
SLVERR. This is achieved by mapping PSLVERR to the AXI signals
RRESP[1] for reads and BRESP[1] for writes.
 From AHB to APB PSLVERR is mapped back to HRESP = ERROR for
both reads and writes. This is achieved by mapping PSLVERR to the AHB
signal HRESP[0].
OPERATING STATES
Figure shows the operational activity of the APB.

Figure : State diagram

The state machine operates through the following states:
IDLE
This is the default state of the APB.
SETUP
When a transfer is required the bus moves into the SETUP state, where the
appropriate select signal, PSELx, is asserted. The bus only remains in the SETUP
state for one clock cycle and always moves to the ACCESS state on the next rising
edge of the clock.

ACCESS
The enable signal, PENABLE, is asserted in the ACCESS state. The address, write,
select, and write data signals must remain stable during the transition from the SETUP to
ACCESS state.
Exit from the ACCESS state is controlled by the PREADY signal from the slave:
  If PREADY is held LOW by the slave then the peripheral bus remains in the
ACCESS state.
 If PREADY is driven HIGH by the slave then the ACCESS state is exited
and the bus returns to the IDLE state if no more transfers are required.
Alternatively, the bus moves directly to the SETUP state if another transfer
follows.
AMBA 3 APB signals:
Table : Lists the APB signal descriptions.
PROGRAM:

`include "apb_tx.sv"
`include "apb_interface.sv"
`include "apb_static.sv"
`include "apb_slave.sv"
`include "apb_gen.sv"
`include "apb_drv.sv"
`include "apb_mon1.sv"
`include "apb_mon2.sv"
`include "ref_model.sv"
`include "apb_sbd.sv"
`include "apb_cov.sv"
`include "apb_env.sv"
`include "apb_program.sv"
`include "top.sv"
//Tob module
module top;
reg pclk;
reg prst_n;
apb_env env;
apb_intf pif(.pclk(pclk),.prst_n(prst_n));
apb_slave dut(.pclk(pif.pclk),
.prst_n(pif.prst_n),
.paddr(pif.paddr),
.psel(pif.psel),
.penable(pif.penable),
.pwrite(pif.pwrite),
.pwdata(pif.pwdata),
.pready(pif.pready),
.prdata(pif.prdata),
.pslverr(pif.pslverr)
);

initial begin
apb_static::vif = pif;
end

initial begin
env = new();
env.run();
end

initial begin
pclk = 0;
forever #5 pclk = ~pclk;
end
 initial begin
// $value$plusargs("testname=%s",apb_static::testname);
end

initial begin
prst_n = 0;
pif.paddr = 0;
pif.psel = 0;
pif.penable = 0;
pif.pwrite = 0;
pif.pwdata = 0;
repeat(2) @(posedge pclk);
prst_n = 1;
end

initial begin
#2000;
$finish;
end
endmodule

//environment
class apb_env;
apb_gen gen;
apb_drv drv;
apb_mon1 mon1;
apb_mon2 mon2;
apb_sbd sbd;
apb_cov cov;
apb_ref ref_;

function new();
 gen = new();
drv = new();
mon1 = new();
mon2 = new();
sbd = new();
cov = new();
ref_ = new();
endfunction

task run();
fork
gen.run();
drv.run();
mon1.run();
mon2.run();
sbd.run();
cov.run();
ref_.run();
join
endtask
endclass

//generator
class apb_gen;
apb_tx tx;
int addr_Q[$];

task run();
for(int i = 0;i<30;i++)begin
tx = new();
assert(tx.randomize() with {paddr inside{[18:21]};});
if(tx.pwrite) addr_Q.push_back(tx.paddr);
 addr_Q.shuffle();
if(!tx.pwrite) tx.paddr = addr_Q.pop_back();
//tx.print("generator");
apb_static::gen2drv.put(tx);
end
for(int i = 0;i<0;i++)begin
tx = new();
assert(tx.randomize() with {paddr inside{[100:200]};pwrite == 0;});

//tx.print("generator");
apb_static::gen2drv.put(tx);
end
endtask
endclass

//driver
class apb_drv;
apb_tx tx;
virtual apb_intf vif;

task run();
vif = apb_static::vif;
forever @(negedge vif.pclk)begin
if(vif.prst_n)begin
idle_phase();
apb_static::gen2drv.get(tx);
drive_tx(tx);
// tx.print("bfm");
end
end
endtask
 task drive_tx(apb_tx tx);
setup_phase(tx);
access_phase(tx);
endtask

task setup_phase(apb_tx tx);

vif.paddr <= tx.paddr;
vif.pwrite <= tx.pwrite;
vif.psel <= 1;
if(vif.pwrite) vif.pwdata <= tx.pwdata;
if(!vif.pwrite) tx.prdata <= vif.prdata;
endtask

task access_phase(apb_tx tx);

@(negedge vif.pclk)begin
vif.penable <= 1;
do
#1;
while(vif.pready != 1);
end
endtask

task idle_phase();
vif.penable <= 0;
vif.psel <= 0;
endtask

endclass

//monitor1
class apb_mon1;
apb_tx tx;
 virtual apb_intf vif;

task run();
vif = apb_static::vif;
forever @(negedge vif.pclk)begin
#1;
if(vif.psel&&vif.penable)begin
tx = new();
tx.paddr = vif.paddr;
tx.pwrite = vif.pwrite;
tx.pwdata = vif.pwdata;
apb_static::mon12ref.put(tx);
apb_static::mon12cov.put(tx);
end
end
endtask
endclass

//monitor2
class apb_mon2;
apb_tx tx;
virtual apb_intf vif;

task run();
vif = apb_static::vif;
forever @(posedge vif.pclk)begin
#1;
if(vif.psel&&vif.penable&&!vif.pwrite)begin
tx = new();
tx.paddr = vif.paddr;
tx.pwrite = vif.pwrite;
tx.prdata = vif.prdata;
 apb_static::mon22sbd.put(tx);
end
end
endtask
endclass

//reference model
class apb_ref;
reg[31:0]mem[(2**25)-1:0];
apb_tx tx;
task run();
forever begin
apb_static::mon12ref.get(tx);
if(tx.pwrite)begin
mem[tx.paddr] = tx.pwdata;
end
else begin
tx.prdata = mem[tx.paddr];
apb_static::ref2sbd.put(tx);
end
end
endtask
endclass

//scoreboard
class apb_sbd;
apb_tx tx,tx1;
int loop,loop1;

task run();
forever begin
apb_static::ref2sbd.get(tx);
 apb_static::mon22sbd.get(tx1);
// tx.print("ckr");
compare_tx();
end
endtask

task compare_tx();
if(tx.prdata == tx1.prdata)begin
$write($time,"READ DATA FROM REFERANCE MODEL
= %h\t",tx.prdata);
$write("READ DATA FROM DESIGN = %h\t",tx1.prdata);
$write("READ DATA MATCHING\n");
end
else begin
$write($time,"READ DATA FROM REFERANCE MODEL
= %h\t",tx.prdata);
$write("READ DATA FROM DESIGN = %h\t",tx1.prdata);
$write("READ DATA NOT MATCHING\n");
end
endtask
endclass

//tx
class apb_tx;
randc bit[31:0] paddr;
rand bit penable;
rand bit pwrite;
rand bit[31:0] pwdata;
rand bit[31:0] prdata;
rand bit pslverr;

function void print(string s = "");

 $display("###########*****%s******#############",s);
$display("paddr = %d",paddr);
$display("penable = %d",penable);
$display("pwrite = %d",pwrite);
if(pwrite)begin
$display("write_phase");
$display("pwdata = %h",pwdata);
end

if(!pwrite)begin
$display("read_phase");
$display("prdata = %h",prdata);
end
$display("pslverr = %d",pslverr);
endfunction
endclass

//interface
interface apb_intf(input logic pclk,prst_n);
logic [31:0] paddr;
logic pwrite;
logic psel;
logic penable;
logic pready;
logic [31:0] pwdata;
logic [31:0] prdata;
logic pslverr;

covergroup apb_cg1(ref logic[31:0] A,int a,int b)@(pwrite);

PADDR:coverpoint A{
bins addr_b1[] = {[a:b]};
 }
endgroup

int a = 1;
int b = 99;
//always@(pwrite)$info("paddr = %d",paddr);
apb_cg1 cg1 = new(paddr,a,b);

endinterface
//program
typedef enum {A,B,C,D}alpha;
program apb_program;
apb_env env;
// bit[2:0] y;
bit c = 1;
alpha y1;
alpha value[$] = {A,B,C};

initial begin
// env = new();
y_f(3);
// env.run();
end
covergroup cg4(ref bit[2:0]y);
Y:coverpoint y {}
endgroup
covergroup cg5;
Y1:coverpoint y1 {}
endgroup
 initial begin
static cg5 cg5_inst = new();
foreach(value[i])begin
y1 = value[i];
cg5_inst.sample();
end
end

function void y_f(bit[2:0] a);

static cg4 cg4_inst = new(a);
cg4_inst.sample();
endfunction

endprogram

//slave
module apb_slave(pclk,prst_n,paddr,psel,penable,pwrite,pwdata,pready,prdata,pslverr);
input pclk,prst_n;
input [31:0] paddr;
input psel;
input penable;
input pwrite;
input [31:0] pwdata;
output pready;
output reg [31:0] prdata;
output reg pslverr;
reg [31:0] mem [(2**25)-1:0];

assign pready = psel&&penable;

always@(posedge pclk)begin
if(!prst_n)begin
prdata = 0;
 pslverr = 0;
end
else begin
if(psel)begin
if(penable)begin
if(pwrite)begin
mem[paddr] <= pwdata;
end
if(!pwrite)begin
prdata <= mem[paddr];
end
end
end
end
end
endmodule

//static
class apb_static;
static mailbox gen2drv = new();
static mailbox mon12ref = new();
static mailbox ref2sbd = new();
static mailbox mon22sbd = new();
static mailbox mon12cov = new();
static virtual apb_intf vif;
static string testname;
endclass

//cov
class apb_cov;
apb_tx tx = new();
event e;
bit writeQ[$];
bit readQ[$];
bit temp,temp1;

covergroup apb_cg;
PADDR:coverpoint tx.paddr{
bins addr_b1[10] = {[1:20]};
bins addr_b2 = {[101:200]};
bins addr_b3 = {123};
bins addr_b5 = default;
ignore_bins addr_b4 = {0};
}
PWDATA:coverpoint tx.pwdata{
option.auto_bin_max = 20;
}
CROSS:cross PADDR,PWDATA;

PART_SELECT:coverpoint tx.prdata[31:29]{
option.auto_bin_max = 4;
}
endgroup

covergroup apb_cg2;
WRITE_READ: coverpoint tx.pwrite {
}
WRITE_READ1: coverpoint !tx.pwrite {
}
CROSS_WR_RD:cross WRITE_READ,WRITE_READ1;
endgroup
 covergroup apb_cg3;
endgroup

function new();
apb_cg = new();
apb_cg2 = new();
endfunction

task run();
forever begin
apb_static::mon12cov.get(tx);
// tx.print("cov");
->e;
apb_cg.sample();
apb_cg2.sample();

end
endtask
endclass

PROCEDURE:
 The modelsim is opened. In the file menu new project is selected.
 In new project wizard name is mentioned then in new project wizard device
properties simulator is selected and finish is chosen.
 In project, new source-select type, verilog module is chosen and file name is given
then the program for digital circuits have been designed and saved.
 Syntax is verified by using the check syntax option in process navigator bar.
 Simulation is done by selecting behavioral simulation from source window and the
corresponding file is selected.
 Then simulator is chosen and the simulated output waveform will
be generated.
PRE LAB QUESTIONS:
1. What is APB protocol?
2. What is APB clock?
3. What is meant by i2c protocol?
4. What is difference between i2c and SPI protocol?
5. What is the difference between i2c and UART?
6. What is AXI protocol?

POST LAB QUESTIONS:

1. How does AXI interconnect work?
2. What are some of the benefits of UVM methodology?
3. What are some of the drawbacks of UVM methodology?
4. Explain the concept of Agent in UVM methodology.
RESULT:

CORE-COMPETENCY LEARNED:

MARKS ALLOCATION

Marks Marks
Details
Allotted Awarded
Preparation 20
Conducting 20
Calculation / Graphs 15
Results 10
Basic understanding (Core competency learned) 15
Viva 10
Record 10
Total 100

Repetition: less 25% of the total marks awarded as above.

Signature of faculty