1.

a) Write Verilog program for 2 to 4 decoder realization using NAND gates only (structural model) along with
test bench and verify the design.
b) Write verilog code to interface a Stepper motor to FPGA and to run the stepper motor 50 steps in
anticlockwise direction.

2.a) Write Verilog program for 8 to 3 encoder with priority (behavioural model) along with test bench and
verify the design.
b) Write a verilog code to interface a DC motor to FPGA and change its speed and direction.

3.a) Write Verilog program for 8 to 3 encoder without priority (behavioural model) along with test bench
and verify the design.
b) Interface a DAC to FPGA and write verilog code to generate Sine wave of frequency F KHz. Modify
the code to down sample the frequency to F/2 KHz. Display the Original and down sampled signals
by connecting them to an oscilloscope.

4.a) Write Verilog program for 8 to 1 multiplexer using case statement along with test bench and verify
the design.
b) Write a verilog code to interface a DC motor to FPGA and change its speed and direction.

5.a) Write Verilog program for 8 to 1 multiplexer using if statements along with test bench and verify the design.
b) Interface a DAC to FPGA and write verilog code to generate Sine wave of frequency F KHz. Modify the
code to down sample the frequency to F/2 KHz. Display the Original and down sampled signals by
connecting them to an oscilloscope.

6.a) Write Verilog program for 4-bit binary to gray converter using 1-bit gray to binary converter 1-bit adder
and subtractor along with test bench and verify the design.
b) Write verilog code to interface a Stepper motor to FPGA and to run the stepper motor 50 steps in clockwise
direction.

7.a) Write Verilog program for a full adder and add functionality to perform logical operations of XOR, XNOR,
AND and OR gates along with test bench and verify the design.
b) Write a verilog code to interface a DC motor to FPGA and change its speed and direction.
 8.a) Write Verilog program for SR flip flop along with test bench and verify the design.
b) Interface a DAC to FPGA and write verilog code to generate Sine wave of frequency F KHz. Modify the
code to down sample the frequency to F/2 KHz. Display the Original and down sampled signals by
connecting them to an oscilloscope.
9.a) Write Verilog program for 4-bit BCD synchronous counter along with test bench and verify the design.
b) Write verilog code to interface a Stepper motor to FPGA and to run the stepper motor 50 steps in
clockwise direction.

10.a) Write Verilog code for counter with given input clock and check whether it works as clock divider performing
division of clock by 2, 4, 8 and 16. Verify the functionality of the code.
b) Write a verilog code to interface a DC motor to FPGA and change its speed and direction.

11.a) Write Verilog 32-bit ALU shown in figure below and verify the functionality of ALU by selecting appropriate
test patterns. The functionality of the ALU is presented in Table 1.

b) Interface a DAC to FPGA and write verilog code to generate Sine wave of frequency F KHz. Modify the code
to down sample the frequency to F/2 KHz. Display the Original and down sampled signals by connecting them
to an oscilloscope.

12.a) Write Verilog program for JK flip flop along with test bench and verify the design.
b) Interface a DAC to FPGA and write verilog code to generate Sine wave of frequency F KHz. Modify the
code to down sample the frequency to F/2 KHz. Display the Original and down sampled signals by
connecting them to an oscilloscope.

13.a) Write Verilog program for D flip flop along with test bench and verify the design.
b) Write a verilog code to interface a DC motor to FPGA and change its speed and direction.