Exercise of

FPGA-Based Digital System Design

Prof. C. Abbate - A.A. 2015/2016

The BPSK Modulator

Introduction
In this exercise a BPSK modulator on FPGA will be simulated and realized. The schematic of the
circuit is reported in the next picture. Please use a new folder MODEM_BPSK for the project.

Two additional outputs are added: a carrier synchronization (CarrierS) and a bit synchronization
(Carrier4). We have assumed that the bit synchronization takes place every 4 carrier periods.
Moreover the phase variation is forced every bit variation by using an additional DFF.
Please, by using Matlab, realize a ROM with 4bit input and 4bit output. Design the frequency
divider in order to have an output frequency of 1700Hz.

Project Simulation
Please write a Verilog test beng file on order to simulate de project.
A typical waveform is reported in the next picture.

Experimental Verification of the Project.

As an example you can assign the pin of FPGA as:
1) Pin 16= input sclr (pin connected to the switch 6);
2) Pin 15= input data (pin connected to the switch 5);
3) Pin 64= system clock;
4) Pin 51= CarrierS auxiliary output (Pin 38 of J12 connector)
5) Pin 53= Carrier4 data synchronization (available on Pin 36 of connector J12).
Use additional outputs (CEneg and CSneg) for the DAC operation.
Please, use the auxiliary LEDs in order to have a debug.