DBNS Filter

Final report

May 3, 2004

Group 12

Mette Hammer

Andrew Ostman

Ray Maleh

Technical Faculty Advisor: Prof. Hongbin Li

I pledge my honor that I have abided by the Stevens Honor System

Table of Contents

DBNS Filter ........................................................................................................................ 1

Final report.................................................................................................................. 1
Table of Contents........................................................................................................ 2
Abstract ............................................................................................................................... 3
Acknowledgments............................................................................................................... 4
Implemented prototype ....................................................................................................... 5
Introduction................................................................................................................. 5
Prototype Specification....................................................................................................... 6
Flowchart representing the DBNS filter: .................................................................... 8
Flow chart illustrating the DBNS algorithm within the FPGA board: ....................... 8
Flowchart of the Binary to DBNS Converter is:......................................................... 9
Circuit diagram of the entire project:........................................................................ 10
Prototype Performance and Evaluation ............................................................................ 13
Conclusion ........................................................................................................................ 16
Follow- On Ideas............................................................................................................... 17
References......................................................................................................................... 19
Appendixes ....................................................................................................................... 20
Appendix A: Spring Gantt Chart .............................................................................. 21
Abstract

The purpose of this project is the design of a low power and computationally

efficient hearing aid. Any positive real number can be approximated using integral

exponents. The operation of multiplication can be reduced into addition. Since integers

are being used, extra computation time is saved. This is an advantage over typical

logarithmic number systems. The DBNS algorithm can be extremely useful in the design

of signal processing devices such as hearing aids and/or DSP processors, where low

power utilization is a priority.

Acknowledgments

Senior Design group 12 would like to acknowledge the support and

assistance of Professor Hongbin Li as our senior design advisor. We would also like to

take this moment to thank Professor Tewksbury for allowing us the usage of an FGPA

board for our prototyping needs. Were it not for the permission to use this board, the

group would have been completely unable to further the project, or even develop a

viable design.
Implemented prototype

Introduction

The purpose of this project is the design of a low power and computationally

efficient hearing aid. Any positive real number can be approximated using integral

exponents. The operation of multiplication can be reduced into addition. Since integers

are being used, extra computation time is saved. This is an advantage over typical

logarithmic number systems. Binary to DBNS conversions are done with the use of a

bijective lookup table. It is then applied to an FIR filter.

In terms of the prototype design, this model is implemented using VHDL that is

downloaded onto a Spartan2 FPGA board. 8 bit digital input is fed through a standard PC

parallel port onto the FPGA board, after which it is processed by the DBNS FIR filter

algorithm. The output is then fed through a digital to analog converter, which feeds the

resulting signal to a PC soundcard for playback.

The DBNS algorithm can be extremely useful in the design of signal processing devices

such as hearing aids and/or DSP processors, where low power utilization is a priority.
Prototype Specification

The DBNS digital filter that was realized in this project operated as follows:

First, an 8 bit digital stream of music was output from the parallel port of a PC with the

help of a MatLab routine written for this purpose. This output was fed into transistors

that acted as switches for 8 on the input pins of the FPGA board, which was the

fundamental processing unit of the filter. In addition, a 12 kHz external clock, which was

implement using a 555-timer chip, was fed into one of the external clock pins of the

FPGA board.

The internal code of the FPGA board waited for every positive edge of the

clock to latch the input entering from the parallel port of the PC. And every time new

data was latched, the old data was moved to another memory location. This is how the

unit delays were implemented in the FIR filter design. The prototype model featured a 4

tap impulse response, thus at any given instant of time, values for x[n], x[n-1], x[n-2], and

x[n-3] were all stored within the board’s memory. Since we only used symmetric filters

in order to ensure a linear phase response, we had two binary adders calculating the sums

x[n] + x[n-3] and x[n-1] + x[n-2].

These two sums were multiplied by the tap coefficients h0 and h1

respectively using the DBNS algorithm, which was programmed into the FPGA board.

To perform a multiplication, we took the magnitudes of both multiplicands and converted

them into binary and ternary exponents using a 7 bit lookup table. The output of the table
was an 8 bit ternary exponent and a 9 bit binary exponent. The most significant bit of

each output reflects its sign. Also, the signs of both multiplicands were used to generate

the 2 bit DBNS sign.

Now the binary exponents of both multiplicands were added as were the

ternary exponents. The result is a 9 bit ternary exponent and a 10 bit binary exponent.

The sign bits of the two multiplicands were used as inputs in a four variable logic

function that returned the 2 sign bits of the product of the multiplicands.

The resulting 9 bit ternary exponent and the 10 bit binary exponent were

input into a 9 bit lookup table, which generated a standard 10 bit binary output. A sign

bit was generated from the sign bits of the product in DBNS format. Then the products

from the taps were added to produce the final result, which was truncated to 8 bits in such

a way that was consistent with the magnitude of the tap coefficients. The output, which

was taken from 8 of the I/O pins of the FPGA board, were run through a D/A converter,

which was constructed entirely out of resistors.

Then, the analogue output was run through a capacitor to kill the DC

component of the output and then fed into the line-in jack of a PC soundcard for

playback.
Flowchart representing the DBNS filter:

Flow chart illustrating the DBNS algorithm within the FPGA board:
Flowchart of the DBNS to Binary Converter:

Flowchart of the Binary to DBNS Converter is:

Circuit diagram of the entire project:
The following is a list of components used in creating the DBNS filter prototype:

• XSA V1.2 FPGA Board (thanks to Prof. Tewksbury)

• 1 PC (thanks to Ray)

• 1 Breadboard (thanks to Microprocessor Lab)

• 555 Timer Chip (thanks to Newark Electronics)

• 8 NPN Switching Transistors (Thanks to Radio Shack)

• 2 Parallel Port Cables (Thanks to Ray and Prof. Tewksbury)

• 1 Parallel Port to Breadboard Connector (Thanks to Ray)

• 17 22k resistors (thanks to Radio Shack)

• 9 10k resistors (thanks to Radio Shack)

• 9 1k resistors (thanks to Radio Shack)

• 8 4.7k resistors (thanks to Radio Shack)

• 2 4k resistors (thanks to Microprocessor Lab)

• 5k potentiometer (thanks to Microprocessor Lab)

• 10 uF capacitor (thanks to Microprocessor Lab)

• 22 uF capacitor (thanks to Ray)

• Wires (thanks to Microprocessor Lab, Ray, and Radio Shack)

• The VHDL code for this project can be found at the homepage:

http://koala.ece.stevens-tech.edu/sd/archive/03F-04S/websites/grp12/
 As for tests to evaluate the prototype performance, we were unable to get

any physical tests running. The group attempted to write some code to sample the output

from the FPGA board that is entering the soundcard of the PC. However, when this code

was run, the MatLab routine that was writing music data to the parallel port could not run

fast enough. Unfortunately, we were not able to work around this problem in time.

Given more time, the group would have considered writing assembly code

to output data so that output speed would not be an issue. As a result, the prototype

performance could only physically be evaluated in a qualitative manner. However,

theoretical tests based on out physical implementation could and were carried out.

MatLab was used to perform these theoretical tests. More on this will be presented in the

next subsection.

Prototype Performance and Evaluation

As mentioned above, due to computer software issues, the group was not

able to measure the output of the DBNS filter without interfering with the MatLab script

that was outputting sound data to the parallel port. As a result, only qualitative and

theoretical can be presented here.

For the qualitative analysis, the output was satisfactory given that we were

effectively processing using 7 bit precision. However, the output was too noisy for most

applications. In an industrial application, at least 32 or 64 bits would be required.

Unfortunately, our FPGA board had very limited resources and thus, the group was

forced to use only 7 bits. The performance appeared to be fast since no multiplications

were taking place. Binary additions and lookup operations are practically free in terms of

a time cost. Another negative observation was the fact that the filter skipped a lot, much

like a CD player does. The reason for this was because of timing issues in the software

that fed the output to the parallel port.

The filter was tested while first operating as a low pass filter and then as a

high pass filter. As a low pass filter, the performance was satisfactory and the group was

able to understand the lyrics of the music that was outputted. On the other hand, as a

high pass filter, the quantization noise was unacceptable, and as a result, the output signal

was very weak. This result was expected since quantization noise is typically high

frequency in nature. This testing indicates that a DBNS filter should only be used for low

pass or band pass applications. If a high pass application is desired, then the sampling

rate must be increased so that the frequencies of interest are significantly below the

Nyquist frequency.

For the theoretical results, we performed a comparison between software

generated versions of our prototype model and a standard 7 bit FIR filter using the same

tap coefficients. A plot that compares the mean square error in both cases is shown

below:
 With no noise, the normal FIR filter far surpasses ours. However, there is

no such thing as a noise-free environment. Also, as power increases, we see a faster

deterioration of the standard FIR filter. Unfortunately, our model never does beat the

standard design. However, the DBNS model does use less power. Also, had we used a

hybrid (2 DBNS digit) design, the performance of our filter would be much better. The

reason for this is because the excessive error is due to the quantization noise. In the paper

“The Mathematics of DBNS Filtering”, Maleh, Ostman, and Hammer showed that the

hybrid design squares the error, thus doubling the noise attenuation in dB. Thanks to our

very small FPGA board, we could not realize this improved design. Overall, the DBNS

filter poses a tradeoff issue. One will have to accept additional quantization noise in

exchange for speed and lower power consumption.

 In terms of the prototype model capabilities compared to the model

proposed in the fall report, a lot of features had to be eliminated once again thanks to our

limited resources. Our original design called for an 8 tap filter, but the group had to

reduce this to 4 taps. In addition, we had to eliminate the adaptive echo equalization

filter that we originally had envisioned. It was our conclusion that our original design

concept was too ambitious given the fact that the DBNS concept is still extremely new.

However, we were quite successful in showing that an FIR filter that utilizes the double

base number system could be realized.

Conclusion

To surmise, given more time, the group would have considered writing

assembly code to output data so that output speed would not be an issue. As a result, the

prototype performance could only physically be evaluated in a qualitative manner.

However, theoretical tests based on out physical implementation could and were carried

out. Our original design concept was too ambitious given the fact that the DBNS concept

is still extremely new. However, we were quite successful in showing that an FIR filter

that utilizes the double base number system could be realized.

Follow- On Ideas

The project could be improved by finding and create other applications, for

example creating a filter for a phone. More advanced filter theory could be utilized, for

example the Wiener-Hopf algorithm. The DBNS theory itself is, we believe, pretty

exhausted, but the applications and uses for the filter are still interesting.

Implementation of the filter in another application could be a topic for a new

project. However, it will not be very unique as the DBNS is by now so thoroughly

researched. The project could be extended if there were larger boards available and a

newer idea for its usage, for example a phone. One could extend the DBNS filter to

involve different signal processing, for audio communications, for instance. It could also

somehow be integrated to a standard DSP board to replace multiplication

Be very careful with whom you choose to create your Senior Design group.

It is probably a good idea NOT to team up with your closest friends, as when you work

with people you do not know very closely instills another kind of respect.

Define your project as early as possible! Start working on it right away,

when you are the most motivated. If you don't feel motivated from the beginning, it is

probably not going to get better later! Try to create a passion for the work, or at least an

interest and it will be so much easier.

 Believe in your capability. You and your group mates can do much more

than you believe. Utilize all your available resources, all from your professors to your

social circle!
References
Note: All these research papers can be found at out homepage:

http://koala.ece.stevens-tech.edu/sd/archive/03F-04S/websites/grp12/

[1] V.S. Dimirov, GA. Jullien, W.C Miller; “Theory and Applications for a
Double-Base Number system” Computer Arithmetic, 1997. Proceedings,
13th IEEE Symposium on , 6-9 July 1997, Page(s): 44 -51

[2] Jullien, G.A.; Dimitrov, V.S.; Li, B.; Miller, W.C.; Lee, A.; Ahmadi, M.;
“A hybrid DBNS processor for DSP computation“
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE
International Symposium on, Volume: 1, 30 May-2 June 1999
Page(s): 5 -8 vol.1

[3] Eskritt, J.; Muscedere, R.; Jullien, G.A.; Dimitrov, V.S.; Miller, W.C.;
“A 2-digit DBNS filter architecture”
Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on 11-
13 Oct. 2000; Page(s): 447 -456

[4] Oppenheim, Willsky, Nawab; “ Signals and Systems”, 2/e;

Prentice Hall, Upper Saddle River, New Jersey 07458; 1997

[5] Oppenheim, Schafer, Buck; “Discrete-Time Signal Processing”, edition 2;

Prentice Hall, Upper Saddle River, New Jersey 07458; 2000

[6] Mitra; “Digital Signal Processing A Computer-Based Approach”, Second

Edition; McGraw Hill; New York, New York 10020; 2001

[7] Parhi, “VLSI Digital Signal Processing, Design and Implementation”

Wiley 605 Third Ave. New York, New York 10158-0012, 1999

[8] Maleh, Ostman, Hammer; “The mathematics of DBNS Filtering” Stevens

Institute of Technology, Hoboken, New Jersey: November 28, 2003

[9] Ostman, Hammer; “DBNS Implementation”. Stevens Institute of

Technology, Hoboken, New Jersey: December 5, 2003

[10] Ostman; “Gain Filter Realization”. Stevens Institute of Technology

Hoboken, New Jersey: December 3, 2003
Appendix
A: Spring 2004 Gantt chart
Appendix A: Spring Gantt Chart