Professional Documents
Culture Documents
BY
Suraj Chaudhary
Department of Electronics & Instrumentation
KIET Group of Institutions,Ghaziabad
CONTENT
• Introduction
• Working
• Need of DSP
• Elements of DSP
• Types of architecture
• Function
• Application
Digital Signal Processor
4.Our ears are sensitive to sound, our eyes are sensitive to light,
and so on.
7.Our brains not only analyze the information received, but also
make decisions using this data.
·Digitize these signals (i.e., convert them from analog to digital using an
Why Do We Need Digital Signal Processors?
Why Do We Need Digital Signal Processors?
• Data Memory:
– Stores the information to beprocessed
• Compute Engine:
– Performs the math processing, accessing the program from the Program Memory and
the data from the DataMemory
• Input / Output:
– Serves a range of functions to connect to the outsideworld
Types of Architecture
Super/ Modified
Harvard HarvardArchitecture
Architecture
Von
Neumann
Architecture
Von Neumann Architecture
Instruction
& CPU
Data Data Bus
Harvard Architecture
Address
Address Bus
Bus
Program Data
Memory CPU Memory
Data Bus Data Bus
Which Architecture is Best Suited for DSP?
1.Common general-purpose personal computers use processors designed with the von
Neuman architecture while the Harvard architecture is more commonly used in
specialized microprocessors for real-time and embedded applications.
3. Many signal and image processing applications require fast, real-time machines.
4.The drawback to using a true Harvard architecture is that since it uses separate
program and data memories, it needs twice as many address and data pins on the chip
and twice as much external memory. Unfortunately, as the number of pins or chips
increases, so does the price.
Which Architecture is Best Suited for DSP?
An elegant solution:
Two (or more) separate buses for program and data are usedinternally.
In one clock cycle, the program information flows on the pins, and
In the second cycle, data follows on the samepins.
Program and data information is then routed onto separate internal program and
data buses. Such machines are called modified Harvard architecture processors
because
the internal architecture is Harvard
external architecture is von Neuman.
• 40 bit ALU
• 2- 40 bit accumulators ACCA& ACCB
• Barrel shifter
• 17X17 bit multiplier
• 40 bit adder
• CSSU-Compare, Select & store unit
• Exponent Encoder
• Data Address generation
• Program & address generation unit
ALU
• 40 Bit ALU
• Wide range of Arithmetic & Logic Operationin
single clock cycle.
• After ALU operation destination of result
– Accumulator or
– Memory
Accumulators
• 40 bit ACCA&ACCB
• To store result for ALU &Multiply/Add.
• Temporary storage for other.
Barrel Shifter
• The barrel shifter can produce a left shift of 0 to 31
bits and a right shift of 0 to 16 bits on the input data.
• The shift requirements are defined in
– the shift count field of the instruction, the shift count field
(ASM) of status register ST1,or
– In the temporary registerT.
Multiplier/Adder Unit
• The multiplier/adder block consists of severalelements: