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Electromechanical Backup
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External environment
System
• 32 BIT UC
• 32 BIT ALU
• 32 BIT DATABUS
• 32 BIT ADDRESS BUS
• 32 BIT INSTRUCTIONS
• Von Neumann model
• 3 stage pipelining- EACH instruction has same size
• 37 register 32 bit each
• 7 operating modes
• 7 Interrupts / Exceptions
• 7 addressing modes
• 3 data formats
• Load/store-based architecture
• Single-cycle instruction execution
• Link register
• Easy decoding and pipelining
• Power-indexed addressing modes
• Fixed 32-bit instruction set
ARM Instruction set
• ARM mostly comes with 2 instruction set
• 32 bit ARM instruction set
• 16 bit thumb instruction set
• In addition to above 2 instructions sets
ARM also implements JAZELLE instruction
set that is used in concepts that use JAVA.
Von neumann model
RISC VS CISC
RISC VS CISC
• At first, this may seem like RISC is much
less efficient way of completing the
operation. Because there are more lines
of code, more RAM is needed to store the
assembly level instructions.
• The compiler must also perform more
work to convert a high-level language
statement into code of this form.
Advantages of RISC
• However, the RISC strategy also brings some very
important advantages. Because each instruction requires
only one clock cycle to execute, the entire program will
execute in approximately the same amount of time as the
multi-cycle "MULT" command.
• These RISC "reduced instructions" require less transistors
of hardware space than the complex instructions, leaving
more room for general purpose registers.
• In RISC Architecture all instructions are same size.
• Because all of the instructions execute in a uniform
amount of time (i.e. one clock), pipelining is possible with
RISC Architecture.
Advantages of RISC
• Separating the "LOAD" and "STORE" instructions
actually reduces the amount of work that the
computer must perform.
• After a CISC-style "MULT" command is executed,
the processor automatically erases the registers.
If one of the operands needs to be used for
another computation, the processor must re-load
the data from the memory bank into a register.
• In RISC, the operand will remain in the register
until another value is loaded in its place.
PIPELINING
PIPELINING
• The four stages are Instruction fetch (IF) from memory, Instruction decode (ID) in
CPU, Instruction execution (IE) in ALU and Result writing (RW) in memory or
Register. Since there are four stages, all the instructions pass through the four stages
to complete the instruction execution.
• Instruction 1 gets completed in t4.
• At t1, while Instruction1 is in IF stage, that being the first stage for any execution,
there is no possibility of overlapping another instruction.
• Thus when Instruction1 moves on to stage 2 (ID)at t2, second instruction enters the
pipeline at IF stage.
• You may observe at t2, there are two stages busy with one each instruction.
Similarly, at t3, I1 and I2 move on to IE and ID stages respectively and I3 enters IF and
so on.
• You may observe that from t4 onwards maximum stages are utilised until the
instruction in-flow.
• After t4, executed instructions leave the pipeline one in each timing state. Refer to
the phase diagram to observe that from timing state t5, one each instruction
completes the execution and out of pipeline paving way for new instructions if any to
enter in.
The family of ARM processors is based on the RISC architecture
• BIU mainly contains the 4 Segment registers, the Instruction Pointer, a pre-fetch queue, and an Address
Generation Circuit.
• Instruction Pointer (IP):
• It is a 16-bit register. It holds offset of the next instructions in the Code Segment.
• IP is incremented after every instruction byte is fetched.
• IP gets a new value whenever a branch instruction occurs.
• CS is multiplied by 10H to give the 20-bit physical address of the Code Segment.
• The address of the next instruction is calculated by using the formula CS x 10H + IP.
The Execution Unit (EU):
• Preprocessing: The source code is processed by a preprocessor, which handles any macro
definitions, file inclusion, and conditional compilation directives.
• Compilation: The preprocessed code is then passed to a compiler, which converts the high-level
code into an intermediate representation called assembly code.
• Assembly: The assembly code is then converted into machine code by an assembler, which
generates an object file that contains the machine code and information needed for linking.
• Linking: The object file generated by the assembler is then passed to a linker, which combines
the object files and resolves any inter-module references to produce a final executable binary.
• Loading: The final binary is then loaded into the memory of the embedded system, ready for
execution by the microcontroller or processor.
• The specific tools used for each step of the compilation process may vary depending on the
embedded system architecture, operating system, and programming language being used.
• Here's a list of some commonly used tools for each step of the compilation process in an embedded
system:
• Preprocessing: The commonly used preprocessor tools are cpp (C Preprocessor) for C language and
cpp for C++ language.
• Compilation: The most commonly used compilers for embedded systems are GCC (GNU Compiler
Collection) and LLVM (Low Level Virtual Machine).
• GCC supports multiple programming languages including C, C++, and Assembly, while LLVM supports
multiple programming languages including C, C++, and Swift.
• Assembly: The commonly used assembler tools are NASM (Netwide Assembler) for x86 architecture
and GAS (GNU Assembler) for multiple architectures.
• Linking: The commonly used linker tools are LD (GNU Linker) and ELF (Executable and Linkable
Format).
• Loading: The commonly used tools for loading the final binary into the memory of the embedded
system are GDB (GNU Debugger) and JTAG (Joint Test Action Group) debugger.
• It's important to note that the specific tools used may vary depending on the architecture, operating
system, and programming language of the embedded system. The tools listed here are some of the
commonly used ones, but others may be used as well.
• Regenerate response
For an embedded system based on an ARM (Advanced RISC Machines) controller, the
following tools are commonly used in each step of the compilation process: