B.E / B.Tech.

PRACTICAL END SEMESTER EXAMINATIONS, NOVEMBER/DECEMBER 2023

Fifth Semester

EC3561 - VLSI LABORATORY

(Regulations 2021)

Time : 3 Hours Answer any one Question Max. Marks 100

Aim/Apparatus Circuit/Program/ Output &

Viva-Voce Record Total
required/Procedure Drawing Results
20 30 30 10 10 100

Design a half adder and full adder circuit using HDL. Simulate it using suitable Software and implement
1.
using FPGA.

Design a half subtractor and full subtractor circuit using HDL. Simulate it using suitable Software and
2.
implement using FPGA.

Design a multiplexer and de-multiplexer circuit using HDL. Simulate it using suitable Software and
3.
implement using FPGA.

Design an encoder and decoder circuit using HDL. Simulate it using suitable Software and implement
4.
using FPGA.

Design any one flip-flop circuit using HDL. Simulate it using suitable Software and implement using
5.
FPGA.

6. Design an 8 Bit Multiplier using HDL. Simulate it using suitable Software and implement using FPGA.

7. Design an 8 bit Adder using HDL. Simulate it using suitable Software and implement using FPGA.

Design a 4 bit Universal Shift Register using HDL. Simulate it using suitable Software and implement
8.
using FPGA.

9. Design a SRAM using HDL. Simulate it using suitable Software and implement using FPGA.

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10. Design a DRAM using HDL. Simulate it using suitable Software and implement using FPGA.

11. Design a ROM using HDL. Simulate it using suitable Software and implement using FPGA.

12. Design Moore FSM using HDL. Simulate it using suitable Software and implement using FPGA.

13. Design Mealy FSM using HDL. Simulate it using suitable Software and implement using FPGA.

Design a 3-bit synchronous up/down counter using HDL. Simulate it using suitable Software and
14.
implement using FPGA.

Design a 4-bit Asynchronous up/down counter using HDL. Simulate it using suitable Software and
15.
implement using FPGA.

Design and simulate a 2-input CMOS AND gate with Manual/Automatic Layout Generation and Post
16. Layout Extraction by performing Pre Layout and Post Layout Simulations and also analyze the Power,
Area and Timing.

Design and simulate a 2-input CMOS OR gate with Manual/Automatic Layout Generation and Post
17. Layout Extraction by performing Pre Layout and Post Layout Simulations and also analyze the Power,
Area and Timing.

Design and simulate a 2-input CMOS NAND gate with Manual/Automatic Layout Generation and Post
18. Layout Extraction by performing Pre Layout and Post Layout Simulations and also analyze the Power,
Area and Timing.

Design and simulate a 2-input CMOS NOR gate with Manual/Automatic Layout Generation and Post
19. Layout Extraction by performing Pre Layout and Post Layout Simulations and also analyze the Power,
Area and Timing.

Design and simulate a 4-bit synchronous counter using Flip-Flops with Manual/Automatic Layout
20. Generation and Post Layout Extraction by performing Pre Layout and Post Layout Simulations and also
analyse the Power, Area and Timing.

Design and simulate a basic Common Source Amplifier circuit using EDA tool and analyze the input
21.
impedance, output impedance, gain and bandwidth by performing Schematic Simulations.

Design and simulate a basic Common Gate Amplifier circuit using EDA tool and analyze the input
22.
impedance, output impedance, gain and bandwidth by performing Schematic Simulations.

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 Design and simulate a basic Common Drain Amplifier circuit using EDA tool and analyze the input
23.
impedance, output impedance, gain and bandwidth by performing Schematic Simulations.

Design and Simulate a CMOS Inverting Amplifier circuit using EDA tool and analyse the input impedance,
24.
output impedance, gain and bandwidth by performing Schematic Simulations.

Design and simulate a 5 transistor differential amplifier circuit using EDA tool and analyse Gain,
25.
Bandwidth and CMRR by performing Schematic Simulations.

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