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1st year PhD Report

Rome, October 21, 2010

Antonio Macera
PhD Student

At the end of the first year of operation, the performed activities are described in this document. Specifically, these activities are divided in two main areas: WideBand Radar Signal design of receivers for Passive Bistatic Radar

Synthesis and Digitization of WideBand Radar Signal


In the framework of signals for highresolution radar systems, the possibility of generating and processing WideBand Signals has been investigated and studied. In this area, technology offers new tools to convert the digital waveform in analogue signal, and viceversa, with very high Sample Rate (up to 1GSPS). High Speed Data Conversion allows to realize a system whit a reduced analogue section, while transferring most of the data processing in the digital domain. Today, High Speed Digital to Analog Converters (DAC) are available that can be used as waveform generators with large bandwidth. In this regard, an interesting topic is the study of algorithms for implementation on a processor for digital synthesis of radar signals. Regarding the section of digitizing, it is very interesting to study the possibility of acquiring Wide Band signals which results in the need to process a large amount of data. In this context, it is important (i) to create some algorithms for the storage and the processing of digital data after analogue to digital conversion, and (ii) to investigate their implementation on FPGA processor. Xilinx e Texas Instruments introduced a new standard for ADC/FPGA connector called FMC. This is very interesting for our studies because we can realize a digitizing with different kinds of ADC without changing the FPGA processor. The main aspects of research in this area will be: Digital Down Conversion on demultiplexed signal Multi channel digitizing (4/8 channel) for Passive Bistatic Radar and array antenna.

Architecture of the Arbitrary Waveform Generator (AWG) System


The AWG is the unit that synthesizes and generates signals around the appropriate IF with bandwidth up to 250MHz. I and Q baseband data are generated by a table code (FPGA device Xilinx Virtex5 LX) and exchanged to an IQ DAC with a sample rate up to 1GSPS. In this design, upconversion function around the IF

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value is obtained in two different steps. Firstly, Digital Up Conversion (DUC) is performend by the DAC device, than a second upconversion is obtained by an analog IQ modulator placed after the DAC device. For this reason, we have selected as DAC a device that, beyond digital to analog conversion, is also capable of applying digital elaboration (as filtering and DUC). The selected DAC device is the DAC5682z provided by Texas Instruments. The IQ Modulator TRF3703 (by Texas Instruments) has been selected as analog IQ modulator. Finally, clock and Local Oscillator (LO) signals that feed the different devices are generated and distributed by the CDCM62005 Clock Generator and the CDCM7005 (clock distributor), respectively. In this scheme, phase coherence is guaranteed by properly locking the different devices. The system will be implemented by evaluation board (see Figure 1).
CDCE62005
Clock Generator and Distributor

EXP High-Speed Digital-to-Analog Converter Module

CDCM7005
PLL and Clock Distributor

Virtex-V
FPGA

DAC5682z
I&Q Digital Data Interpolating 16bit 1GSPS Dual DAC

TRF3703
Q I&Q Modulator RF Output

Xilinx Virtex V Evaluation Kit

EXP Interface
16bit LVDS SPI Clock

Figure 1 Block Diagram AWG

description of the components DAC5682z (see Figure 2) is a dualchannel 16bit 1.0 GSPS DAC with wideband LVDS data input, integrated 2x/4x interpolation filters, onboard clock multiplier and internal voltage reference. The DAC5682Z offers superior linearity, noise, crosstalk and PLL phase noise performance. The DAC5682Z integrates a wideband LVDS port with onchip termination. Fullrate input data can be transferred to a single DAC channel, or halfrate and 1/4rate input data can be interpolated by onboard 2x or 4x FIR filters. Each interpolation FIR is configurable in either LowPass or HighPass mode, allowing selection of a higher order output spectral image. An onchip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.

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Figure 2 Block Diagram DAC5682z

TRF3703 is a lownoise direct quadrature modulator capable of converting complex modulated signals from baseband or IF directly up to RF. The TRF3703 is ideal for high performance direct RF modulation from 400 MHz up to 4GHz. The modulator is implemented as a doublebalanced mixer. The RF output consists of a differential to single ended converter and an RF amplifier capable of driving a singleended 50 load. CDC7005 is a high performance, low phase noise, lowskew clock synthesizer and jitter cleaner that synchronizes the voltage controlled crystal oscillator (VCXO) frequency to the reference clock. The programmable predividers M and N give a high flexibility to the frequency ratio of the reference clock to VCXO. Through the selection of the external VCXO and loop filter components, the PLL bandwidth factor can be adjusted to meet different system requirements. CDCE62005 is a high performance clock generator and distributor featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by onchip EEPROM. The device provides output frequencies up to 1.175 GHz. The clock distribution block includes five individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS).

next steps prototype realization and laboratory tests definition of algorithms for the digital synthesis of wide band radar signals

Architecture of the Digitizer


The Digitizer section is essentially composed by two sub blocks, a FPGA device and an Analog to Digital Converter (ADC) device. In this planning stage, a digitizer that samples signals with bandwidth of 500MHz is not feasible, but the possibility of implementing a parallel Digital Down Conversion and a conventional signal processing for radar on demultiplexed signals will be investigated. Regarding the FPGA, the specific device to be used to elaborate data samples is the Xilinx VirtexVI, that can be considered the state of the art for this kind of application.

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Regarding the ADC, a possible solutions is represented by the ADS62P49, provided by Texas Instruments. Interconnection between FPGA evaluation board and ADC evaluation board can be achieved by the FMCDACAdapter that is the new standard of Texas Instrument and Xilinx high speed connector. The ADS62P49 is a dual channel 14bit A/D converter with sampling rates up to 250MSPS and 800MHz input bandwidth. It combines high dynamic performance and low power consumption. This makes it wellsuited for multicarrier, wide bandwidth communications applications. The architecture of the Digitizer is shown in Figure 3.

Figure 3 Block Diagram Digitizer

next steps prototype realization and laboratory tests definition of algorithms for the digitalization and data storage of wide band radar signals implementation of radar processing in FPGA processor assess the feasibility of replacing the device ADC to obtain a multi channel (4/8 channel) digitizer

Design and implementation of receivers for Passive Bistatic Radar (PBR)


In the framework of research activity on passive radar systems for target detection and localization my activity is mainly focused the hardware section of the system. During this stage of my PhD course, I have worked to improve the performance of some PBR prototypes. First of all, the following requirements for the PBR system have been defined: improvement of system performance in terms of SignaltoNoise Ratio (SNR): exploititation of the dynamics of the Analogue to Digital converter through appropriate sizing of the receiver analog section image rejection and inter channel interference mitigation performance improvement of multichannel cancellation algorithm good removal of direct signal during the processing

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My activities include the study of different architectures for the analogue section of PBR receivers for different broadcast signals. COTS components have been chosen for each prototype system and have been tested in laboratory to verify their behavior. These components have been also tested during experimental acquisition campaigns carried out in an operative area for the different PBR applications.

Design and test of a different prototype receiver architecture for PBR based on FM broadcast signal
Aiming at exploiting the whole 88108 MHz frequency band of the FM radio broadcast, two receiver systems can be developed: WideBandwidth NarrowBandwidth Performed analysis aims at evaluating and comparing the results obtained with the two systems. The study of the signal levels was a prerequisite for the realization of different prototypes. This study was conducted at the Faculty of Engineering in Rome and at Civitavecchia, about 70 km north of Rome. WideBandwidth The wideband approach allows the scan of the entire FM band of 20MHz and the selection of one or multiple radio channels after signal digitalization. The main drawback of this system is the restriction of the dynamics on the single radio channel, because the whole dynamic of the system must take into account the whole FM bandwidth. The main advantage is the ability to use a multifrequency integration approach which enhances the surveillance capabilities of the PBR system. The main points of this activity have been: the definition of different architectures for the analog section of the receiver between the antenna and the digitizer (variable attenuators, amplifier, RF filters) laboratory tests on individual components the verification of the increase in system performance in terms of cancellation and target detection capability (after digital processing) Figure 4 shows the block diagram of the WideBandwidth receiver.

Figure 4 Architecture of the WideBandwidth FMbased PBR receiver

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next steps selection of system components in order to realize a 4 channel receiver. The receiver must be able to handle input signals with different strengths depending on the site selected for tests and acquisition campaigns. NarrowBandwidth The NarrowBandwidth approach includes a signal downconversion stage from RF to IF, a filtering stage for single radio channel selection (200kHz bandwidth), and finally a digitalization stage. This approach improves the signal dynamics on the single channel, but the increase of the analog section of the receiver makes necessary to equalize the signals obtained by digital processing. The main points of this activity have been: the definition of different architectures for the analog section of the receiver between the antenna and digitizer (variable attenuators, amplifier, RF filters, IF filters) laboratory tests on individual components Figure 5 shows the block diagram of the NarrowBandwidth receiver.
NI PXI 5122 NI PXI 5670
(AWG + Upconverter) (ADC)

Figure 5 Architecture of the NarrowBandwidth FMbased receiver

next steps verification of the increase in system performance in terms of cancellation and target detection capability (after digital processing) construction of a multichannel receiver with COTS components

Preliminary tests on WiFi signals


In the framework of research activity on receivers for WiFi signals, I tested a system of down conversion, in order to verify the characteristics of the signals. This activity was preliminary to an acquisition campaign within the European project ATOM. The main points of this activity were: the study of a specific system component: RF2051 double mixer with integrated PLL/VCO the study of possible innovative architectures to produce a lowcost receiver and the selection of proper analog components

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the definition of a frequency plan laboratory test with real DSSS (definire acronimo!) WiFi Signals preliminary tests on I&Q Demodulator for a receiving scheme with a baseband or lowIF signal acquisition Figure 6 shows the block diagram of the test bench.

Figure 6 Architecture of the test bench for WiFi signals

next steps construction of a receiving system for the acquisition of baseband WiFi signals

Design of a multichannel prototype receiver for Space Based Passive Radar


Space Based Passive Radar project aims at the development of a prototypal passive radar system exploiting spacebased transmitter as illuminator of opportunity. Different telecommunication space platforms were selected for this project. Different standards for the transmitted signals are foreseen in LBand and SBand, with maximum bandwidth of 4MHz. The direct power signal is of about 85dBm (value achieved by preliminary experimental measurements carried out at the Faculty of Engineering in Rome, with a single channel receiver NI PXI5600 and satellite active antenna). Stages of design were: identification of a specific frontend: analogue RF and IF filters (different for each platform) definition of a proper frequency plane: single down conversion from RF to 70MHz IF architecture of the downconversion system (see Figure 7), with a total gain of about 83dB (from digitizer and power level preliminary study), and devices selection identification of the digitizer: NI PXI5122 (100 MS/s, 14Bit Digitizer) Architecture of the prototype receiver (single channel)

Figure 7 Architecture of prototype receiver (single channel)

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Noise and signal Levels


RF Filtter 1 Noise In dBm/[BWMHz] Max Sig In [dBm] 1dBcp NF Tot [dB] 3,40 RF Filtter 1 1,40 LNA ZX6033LN NF [dB] Signal Gain [dB] Gain [dB] Bandwidth [MHz] 2,00 -2,00 83,10 5,00 1,10 14,50 -103,61 -85,00 LNA -105,61 -87,00 Amplifier -91,11 -72,50 16,50 5,56 Amplifier ZKL-2R7 5,50 24,40 2,00 -2,00 RF Filtter 2 -66,71 -48,10 17,00 11,87 RF Filtter 2 9,87 Mixer ZX05-43+ 6,80 -6,80 3,07 Amp ZKL-1R5 3,00 41,00 Mixer -68,71 -50,10 Amp -75,51 -56,90 IF Filter -34,51 -15,90 19,00 26,32 IF Filter TriQuint 70 MHz SAW Filter 7,50 -7,50 18,82 Att ZX7631R5-PP+ 12,00 -12,00 6,82 Amplifier ZKL-1R5 3,00 41,00 Att -42,01 -23,40 Amp -54,01 -35,40 IF Filter -13,01 5,60 19,00 45,50 IF Filter TriQuint 70 MHz SAW Filter 7,50 -7,50 38,00 ADC NI PXI 5122 38,00 0,00 ADC -20,51 -1,90

next steps selection of the antenna for the surveillance channel prototype realization and laboratory tests acquisition of real data sets, with dual channel receiver configuration, for Passive Radar Processing performance verification.