A Frequency Agile Implementation for IEEE 802.

22 Using Software Defined Radio Platform

Yahia Tachwali, Mustafa Chmeiseh, Fadi Basma, Hazem H. Refai, Member, IEEE
In the context of spectrum sharing using cognitive radio, IEEE 802.22 air interface [2] was organized in November 2004 to provide wireless services in wireless regional area network using unused TV spectrums. This standard specifies a fixed point to multipoint air interface. The topology of an 802.22 based network consists of a Base station (BS) and a number of associated Consumer Premise Equipments (CPEs). The base station manages the control access which is based on a unique feature of distributed sensing. The CPEs perform the spectrum sensing in order to protect primary users of this spectrum range from interference. There are two types of primary users (sometimes called incumbents) which are TV services and wireless microphones. There are many spectrum sensing techniques that have been proposed. Comprehensive reviews of recent spectrum sensing techniques and dynamic spectrum access can be found in [3-5]. However, the tendency of the research community is to employ spectrum sensing in two stages namely fast sensing and fine sensing. For more information about the coming IEEE 802.22 standards, the reader can refer to [2]. The cognitive radio technology and its potential implementation in IEEE 802.22 standard are still in the initial stage. There are a limited number of cognitive radio implementations presented in literature that are capable of performing a multi-resolution spectrum sensing which was originally introduced in [6,8]. Recent work presented in Globecom07 by Motorola labs has shown a cognitive radio prototype that is capable of performing channel allocation within 20 MHz bandwidth (fine sensing) using spectrum correlation density technique [7]. Another spectrum sensing technique is based on wavelets suggested by Georgia Tech and implemented in [8-9]. Researchers at Berkeley Wireless Research Center have studied the spectrum sensing implementation consideration for cognitive radios in [10-11]. In this work, we present the design and implementation of a cognitive radio based on a software defined radio platform [12]. This cognitive radio is an upgraded version of the transceiver presented in [13] by adding the spectrum sensing capability and frequency switching mechanism in the range of 200 to 900 MHz which is compatible with the coming IEEE 802.22 standard. The fast spectrum sensing is based on energy detection using Welchs periodogram [4] while the fine sensing is feature based using a cyclostationary feature detector [14]. The energy detection technique is fast and can be implemented efficiently using FFTs in an FPGA. Therefore, we have chosen this technique for fast sensing.

Abstract This paper reports the design and implementation of a frequency agile software defined radio platform that is capable of performing a multi-resolution spectrum sensing. A fast spectrum sensing mechanism is implemented based on energy detection and a fine spectrum sensing mechanism is implemented based on feature detection. The platform is capable of switching to different communication channels in a spectrum range of 200-900 MHz which is compatible with IEEE 802.22 air interface. Different design considerations on the software defined radio platform are discussed. This study shows the feasibility of using software defined radio platforms as well as high level system design development tools to implement frequency agile cognitive radios. Index Terms Software defined radio, cognitive radio, 802.22, spectrum sensing, frequency agile.

he severe underutilization of spectrum reported by the Federal Communications Commissions (FCC) [1] has driven the research community into finding alternative solutions to improve the utilization of radio frequency spectrum. Spectrum sensing and sharing techniques using cognitive radios formulate an attractive solution for increasing the utilization of spectrum and enable a whole new class of application. The development of cognitive radio (CR) systems is fast becoming a hot topic in wireless research due to its importance in enabling the spectrum sharing solution. CR system performs computational intensive tasks such as spectrum sensing to detect the unused spectrum and sharing it without interfering with other users. Another task is the spectrum management to capture the best available spectrum for user communication requirements. Also, Spectrum Mobility feature in CR is required to change the frequency of operation if needed. To implement such frequency agile systems, a high computational power and configurability platform is needed. The recent advent of software defined radio (SDR) technology has made it an appealing choice for cognitive radio implementation. A combination of processing engines in SDR such as digital signal processors (DSP) and Field Programmable Gate Arrays (FPGA) can achieve a balance in cost, power, performance, flexibility and reliability.

I. INTRODUCTION

Manuscript received on March 31, 2008. Y.Tachwali, F.Basma, M.Chmeiseh, H.Refai are with the Electrical Engineering Department at the University of Oklahoma, Tulsa, OK 74135 USA. (email: {ytachwali, mustafa.chmeiseh,fadi.basma,hazem}@ou.edu)

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This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE "GLOBECOM" 2008 proceedings.

However, energy detection can not distinguish between the interference and noise. Hence, a feature detector is chosen for fine sensing to compensate for the limited capabilities of energy detectors. To the authors knowledge, this work is the first implementation of a cognitive radio based on software radio platform that is capable of performing a multiresolution spectrum sensing and is compatible with IEEE 802.22 standard. This work formulates a guideline of using software radio platforms based on DSP and FPGAs to implement a cognitive radio for 802.22. The remainder of this paper is organized into the following sections. In section II, an overview of the cognitive radio system and a description of the spectrum sensing and channel switching subsystems are presented. In section III, we present the implementation results. We highlight the design considerations and implementation challenges for our cognitive radio system. In section IV, and section V concludes.
II.

Fig. 1. General block diagram of the cognitive radio system using a software defined radio platform

PLATFORM DESCRIPTION

A. Software Defined Radio Platform Description The cognitive radio is implemented using a modular small form factor (SFF) software defined radio (SDR) platform produced by Lyrtech [12]. Figure 1 shows a simplified hardware block diagram of the SDR platform which consists of three modules: digital signal processing module, data conversion module and RF module. The cognitive modem design is implemented in the digital signal processing module. The other two modules are configurable through a number of control signals generated from the DSP in digital signal processing module. The digital signal processing module uses a Virtex-4 FPGA and DM6446 DMP. The DMP chip features an advanced Very Long Instruction Word (VLIW) DSP portion which is responsible for some signal processing tasks in the transceiver design, and a Reduced Instruction Set Computer (RISC) ARM9 core which is used for running a real-time operating system (RTOS). The data conversion module is equipped with a 125 MSPS, 14-bit dual channel ADC and a 500 MSPS 16-bit dual channel interpolating DAC. It is equipped also with programmable gains at the input and output of the ADC and DAC respectively. This enables the implementation of automatic gain control AGC and transmission power control. The RF module is configured to have either 5 or 20 MHz bandwidth with transmission frequency range of 200-930 MHz and receiving frequency range of 30-928 MHz. This range is compatible with the 802.22 specifications [2].

Interfacing between DSP and FPGA is achieved using different connections. The main bridge between the two processing engines is the Video Processing Sub-system (VPSS) data port, i.e. a DM6446 DSP 16-bit synchronous video data transfer port. The VPSS is composed of the video processing front end (VPFE) and the video processing back end (VPBE), where the VPFE is used as an input interface to the DSP and the VPBE as an output interface from the DSP. The VPSS was adapted to be used on the digital processing module of the SDR platform as an interface to transfer data other than video between DSP and FPGA. In order to emulate video signals, Vsync and Hsync signals are generated by the VPFE of FPGA interface. The FPGA VPBE uses the Vsync and Hsync signals generated by the DSP to synchronize the incoming data transfer. Also, another interfacing method is achieved by custom registers which are shared memory blocks of eight 32-bit words between DSP and FPGA On-Chip Peripheral Bus (OPB). Additional information about the hardware specification can be found in [12]. Based on the software radio platform described, we have developed a cognitive radio platform that is composed of three subsystems: A configurable digital transceiver, spectrum sensing and channel switching subsystems. Generally, the DSP is dedicated for communication and control signaling. The digital signal processing intensive operations are performed in FPGA. Therefore, part of the digital transceiver is implemented in the DSP, while most of the digital transceiver as well as the complete spectrum sensing and channel switching and control subsystems are implemented in FPGA. In the following section, we list a detailed description of the spectrum sensing and channel switching and control subsystems. B. Spectrum Sensing Subsystem The spectrum sensing subsystem operates in one of the two modes namely the fast and fine sensing modes. Figure 2 shows a simplified block diagram of the spectrum sensing subsystem. The heart of the spectrum sensing subsystem is the FFT core provided by Xilinx [15]. The FFT core used in our design computes an N-point forward DFT where N can be

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Detection

Energy Estimation ADC FFT CSD Estimation

Control Interface

Fig. 2. A simplified block diagram of the spectrum sensing subsystem

2^m, m = 3 to 16. The input data is a vector of N complex values represented as bx-bit twos-complement numbers -- bx bits for each of the real and imaginary components of the data sample (bx = 8 to 24). Similarly, the phase factors bw can be 8 -- 24 bits wide. All memory is on-chip using either Block RAM or Distributed RAM. The N element output vector is represented using by bits for each of the real and imaginary components of the output data. In addition the core supports three architecture options which are - Pipelined, Streaming I/O. Allows continuous data processing. - Radix-4, Burst I/O. Offers a load/unload phase and a processing phase; it is smaller in size but has a longer transform time. - Radix-2, Minimum Resources. Uses a minimum of logic resources and is also a two-phase solution. Figure 3 shows a detailed view of the spectrum sensing subsystem and the different control signals used in this model. In the following sections, we describe the sensing modes of this subsystem.

Fast Spectrum Sensing Mode The fast spectrum sensing is based on energy detection by averaging the FFT output amplitude over different cycles. It can be seen from figure 3 that the FFT output is directed to the averaging and CSD estimation blocks. In the averaging block, a preconfigured averaging window length M can be specified. The output of the averaging is loaded into a first input first out memory block (FIFO). The FFT block provides a complete DFT output every N clock cycle where N is the size of FFT. Hence, an averaged FFT output calculated every N.M cycles. While it is possible to have a pipelined implementation of the fast sensing mode that allows an FFT output every N cycles, the decimation operation by M that is performed by the averaging filter is chosen due to some hardware limitations. This point will be explained in the design consideration section. Fine Spectrum Sensing Mode The fine spectrum sensing should outperform the fast sensing mode in terms of frequency resolution and its capability for distinguishing between interference and noise. These capabilities are critical for choosing a valid subchannel between adjacent occupied subchannels within a limited frequency range such as 20 MHz. Feature detectors are used to achieve this capabilities. In our design we have used the cyclostationary feature detector which calculates the cyclic spectral density (CSD) as an indication of redundancy in the signal periodicity that appears in modulated signals. For a given FFT output named X(k), the CSD is given by [4]: CSD (k , ) = E X k + X * k (1) 2 2

Fig. 3. A detailed view of the spectrum sensing implementation using Simulink, Xilinx System Generator and Lyrtech development tools.

where is the frequency separation or FFT resolution (also called cyclic frequency). It can be seen from equation (1) that CSD is a two dimensional transform. However, due to hardware and 802.22 spectrum sensing time requirements, the CSD transform is estimated for a limited number of k and . Hence, the CSD estimator is implemented as per the following equation: 1 M CSD (k ) = (2) i=1 X i k + 2 X i* k 2 NM where N is the FFT size, M is the averaging filter size. It can be noted that in case of =0, the CSD output is called power spectrum density which is equivalent to the output calculated in fast sensing mode. At this stage, it was very difficult to meet the real time requirement for CSD estimation over the entire two dimensional plane of cyclic and spectral frequencies. Instead, the CSD operation is performed for k=0 and all values of from N to N. This will reduce the correlation calculations complexity from the order of N2 to 2N. Similar CSD simplification approaches can be found in [17,18].

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C. Channel Switching and Control Subsystems The subsystem is responsible for a number of control tasks. First, it controls the channel frequency switching by adjusting the VCO in the analog RF board. During the fast spectrum sensing mode, this subsystem tunes the VCO so that the cognitive radio receiver scans the whole shared spectrum. The FFT done control signal is used to trigger the increment (or decrement) of the VCO frequency controller. It takes into consideration the averaging length M stored in a shared memory register so that a VCO frequency shifting of 20 MHz (which is the receiver bandwidth defined by the passband filter in the RF board) is performed every M done signals. The second control task is regulating the ADC and DAC programmable analog gains to avoid ADC saturation and control transmission power to manage the signal interference caused by the cognitive radio. The third task is to control the switching between sensing modes and normal communication mode. The control words for VCO and gains are passed to the DSP the shared memory registers. Figure 1 highlights the control signal sent from DSP to the data conversion board and radio board.

Fig. 4. A detailed view of the cognitive radio implementation using Simulink, Xilinx System Generator and Lyrtech development tools.

III.

IMPLEMENTATION RESULTS

The proposed cognitive radio system is implemented on the software defined radio platform developed by Lyrtech [12]. The FPGA model is developed using a system based development tools which are Simlink[16], Xilinx System Generator [14] and Lyrtech development tools. The ADC and FPGA are clocked at 120 MHz. This clock speed is the close to the maximum clock speed for the ADC on the SDR platform. This clock rate will allow to have the IF=fs/4 which has a number of benefits in implementations. First, the down conversion stage can be implemented by a simple multiplexer rather than using expensive embedded multiplier resources in FPGA. Also, it has been shown that the ratio of 4 between fs and fc allow for better detection results using SCD[18]. We have not considered power consumption constraints at the initial design phase of this cognitive radio system. A maximum FFT size of 2K could be achieved with the current design due to limited FPGA resources. Further design optimization especially in the digital modem will allow for higher FFT size. Figure 4 shows a detailed view of the cognitive radio system model.

The cognitive radio spectrum sensing subsystem was tested on the range 200 to 900 MHz. The available antennas at the time of the experiment are not wide range antennas and they are optimized for 450 MHz. Hence, we compensated the degradation in the antenna sensitivity away from 450 MHz by gain scheduling on the adjustable analog amplifiers before the ADC. Figure 5 and 6 show snapshots of the fast spectrum sensing output during the scanning from 200 MHz to 900 MHz using 1K FFT. Two different signals have been generated at three different frequency bins as shown in the figures 5 and 6. The first signal is an analog narrow band signal (pure sinusoid) and the second is a wideband DSSS generated at 5 MHz and 7 MHz. These signals are generated in the frequency bin 440460 MHz, and 500-520 MHz. The frequency span on these plots is from 0 to 62.5 MHz with an increment of 61 KHz.

Wideband signal BPSK-DSSS 5MHz Unmodulated carrier (Pilot tone)

Fig. 5. A snap shot of the fast spectrum sensing result and frequency bin of 440-460.

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Unmodulated carrier (Pilot tone)

Wideband signal BPSK-DSSS 7MHz

Fig. 6. A snap shot of the fast spectrum sensing result and frequency bin of 500-520. IV.

detector for fine sensing is due to its good performance in low SNR environment. Different hardware specifications affect the SNR value at the ADC such as the noise factor parameter of the RF front end and the 1/f noise level as well as the thermal noise level per Hz. The SNR value in the digital domain is governed by the dynamic range of the ADC defined by its bit size. The implementation spectrum detector in this cognitive radio occupies around 6200 slices. The initial results of the detector performance have shown the feasibility of this implementation. Table 1 lists the probability of error and probability of false detection for a carrier and BPSK signal at different low SNR values using SCD detector. The received signal was simulated to guarantee accurate SNR value at the ADC. The BPSK symbol rate is 7.5Msps, the IF level is 30 MHz, and the sampling frequency is 120MHz. V. CONCLUSION In this paper we present the design and implementation of a frequency agile cognitive radio that is compatible with IEEE 802.22. The proposed cognitive radio system is capable of performing fast spectrum sensing along the complete range of the shard spectrum as well as a fine spectrum sensing in a limited frequency range. Different design considerations for spectrum sensing and channel frequency switching subsystem are discussed. This work formulates a guideline for designing a software defined radio based cognitive radio to operate under IEEE 802.22 constraints. It describes a cognitive radio system design and implementation from the RF level to the baseband level. In future work, timing and performance analysis of the design will be explored to optimize the spectrum sensing accuracy and to achieve a minimum channel setup time for the proposed cognitive radio system. ACKNOWLEDGMENT The Authors would like to thank Lyrtech technical support team members for their valuable help and feedback. Special thanks to Mr. Mathieu McKinnon on his help in analyzing the RF receiver sensitivity and capabilities against small SNR signals.
Table1: The probability of detection at 0.1 false alarm probability of SCD based detector at low
SNR values

DISCUSSION AND DESIGN CONSIDERATION

The performance of the cognitive radio system is measured by different parameters that can be categorized into two main categories. The first one is timing based parameters which measures the safety time margins achieved by the cognitive radio design and the timing constraints defined in IEEE 802.22 such as the maximum channel detection time, channel setup time, channel closing transmission time. The other parameter category is sensing accuracy such as the false alarm rate and sensitivity level of the transceiver. Threshold values for energy detection spectrum sensing technique are selected based on a given false detection rate constraint. The timing performance parameters of the cognitive radio system are affected by different hardware elements in the analog and digital parts of the cognitive radio. In the analog part, the settling time of the frequency synthesizer that controls the VCO is an essential element in determining the maximum time required to move from one frequency to another. This frequency adjustment occurs during frequency switching or during the fast spectrum sensing along the complete shared spectrum. From the digital part of the cognitive radio system, the convergence time of the timing synchronizer after switching from one channel to another affects the channel setup time. Another performance defining element is the computational power and memory resources available in hardware to calculate the FFT and perform MAC operations to estimate the CSD and PSD for fine and fast spectrum sensing respectively. In our design, we have chosen to decimate the FFT output due to the maximum VPSS bus speed limitation. The maximum speed from FPGA to DSP is 150 Mbps (16 bits, 75 MHz), while the maximum speed from DSP to FPGA is 75 Mbps (16 bits, 37.5 MHz). The spectrum sensing resolution is mainly governed by several design choices. First of all, the size of the FFT block determines the frequency resolution of the FFT transform and it is limited by available FPGA resources. In our design, the minimum frequency resolution that can be achieved is 30.5 KHz. Another design consideration is the SNR value of the received signal. In fact, the choice of the feature based

Carrier BPSK Signal

SNR=-10dB 0.99 0.998

SNR=-15dB 0.99 0.78

SNR=-20dB 0.8 0.4

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This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the IEEE "GLOBECOM" 2008 proceedings.