Paper ID: 2

2
Title: A 0.0375mm 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring Amplifier Based Integrator in 180nm
CMOS

2
Abstract: This work presents a compact (0.0375mm ), low-power (203.5uW), high-resolution (108.8dB DR) 180nm DT DSM Audio ADC. The
design uses the pseudo-pseudo-differential switched capacitor technique which utilizes single-ended circuits and provides rejection of low-
frequency noise. A single-ended ring amplifier with high equivalent bandwidth is used in conjunction with the proposed merged-adder to relax timing
of the digital circuitry. Unprecedented power-efficiency (188.7dB FoM) and area are achieved.
Subcommittee First Choice: Data Converters
Subcommittee Second Choice: Undecided

Submission Demographics

This paper is being submitted from University

Are you interested in participating in the Demonstration Session at ISSCC? No

Double-Blind Review Process

1. Have you read the Author Instructions and FAQ which outline the double-blind review submission requirements? Yes
I have read the Author Instructions and FAQ.
2. Is your manuscript fully anonymized to hide author and affiliation identities, including PDF metadata, logos on die photos, logos on
printed circuit board photos, etc.? Yes
my manuscript is fully anonymized to hide author and affiliation identities.
3. Did you cite all relevant prior work (including your own) in the third person? Yes
I have cited all relevant prior work in the third person.
4. Did you upload as Supporting Material any work of yours that is related to this submission and has been sent to another
Conference/Journal, but has not been published yet? Did you cite this work in anonymized format according to the Author Instructions?
Failure to adhere to this process may result in removal from accepted paper list even after acceptance. Yes
any work of ours which is related to this submission and has been sent to another Conference/Journal
but has not been published yet
has been uploaded as Supporting Material and has been cited in anonymized format.
5. Please check the following to show you have read and understood:
I understand that, if accepted, I will need to submit an updated version of my paper with author and affiliation data included and references
unblinded.
I understand that, if accepted, my paper will be edited by a Technical Editor who will ensure that my paper is compliant with the ISSCC editorial
guidelines.

Technology

CMOS

Originality

New design and/or architecture

New design methodology
Smallest published
Lowest power dissipation published
Best figure of merit published

Design Status

Chip testing complete, measured data supporting submitted paper

Submission Highlights

Compared to the leading Discrete-Time design implemented in a similar technology, this design reduces power by 2.2x and area by 7.2x. This ADC
uses new circuit concepts which utilize single-ended active blocks. This design in 180nm CMOS occupies the smallest chip area and is 53% of the
area of a comparable 28nm CMOS design. The design exhibits the highest figure-of-merit in state-of-the-art designs with 1.32x better overall
efficiency when compared with the previous leading design.
Introduction

1. Have you clearly highlighted what is the novelty in the reported circuit or architecture? Is the target application clearly described? Yes
2. Have you explained how your circuit or architecture advances the state of the art? If your work is part of a large system, have you
explained how your particular design advances the state-of-the-art as part of that system? Yes
3. Have you compared your results against representative examples from the recent literature? Please clarify and explain using a table, if
possible. Yes
4. Have you included performance in the form of recognized standard metrics (such as PVT sensitivity, area, noise, reliability metrics,
etc)? Yes
5. For power consumption and area measurements, have you clearly stated what blocks or functions are included (or omitted) in the
calculations? Yes
6. The ISSCC committee considers the quality of the referenced citations when judging your paper, does your reference list provide
adequate coverage of the related work (prior work by others and your own work) including papers from previous ISSCC where
applicable? Yes
7. Has your text been reviewed for correct use of grammar, punctuation, and spelling? Yes
9. ISSCC reviews circuit performance based on actual measured results (rather than simulation)-- Are the results clearly stated as
measured or simulated? Yes
10. What is the abstraction level of the primary innovation? System/sub-system implementation, architecture level
Other. Please explain
11. Does your innovation cut across different subcommittees? No
Please list all subcommittees in which your innovation cuts across.

Data Converters

1. We ask that you provide the following measured data in the submitted paper (or in the supplemental material). If you chose not to
provide the data below, please explain why they are not appropriate to document your work.

● Nyquist ADC: SNR, SFDR, SNDR vs. Fin and Fclock; nominal (by design) input sampling capacitance (or resistance) driven by external

signal source; input voltage/current range; output spectrum.

● Oversampling ADC: SNR, SFDR, SNDR vs. Fin and Fclock; OSR; nominal (by design) input sampling capacitance (or input resistance)

driven by external signal source; input voltage/current range; output spectrum.

● Nyquist DAC: SNR (NSD preferred), SFDR (IMD preferred) vs. Fin and Fclock; output current/voltage range; output spectrum; load (e.g. off-

chip 50).
● Oversampling DAC: SNR, SFDR, SNDR vs. Fin and Fclock; OSR; output current/voltage range; output spectrum; load (e.g. 10k ||30pF).

All measured data referenced above is provided in the submitted paper.

2. In what process technology was your device fabricated/measured (e.g. 65nm CMOS)?
180nm CMOS
3. What are the supply and reference voltages used in your device? Please list all voltages and the corresponding sub-blocks (e.g.
reference=0.2V/0.8V, analog=1V, digital=1.8V, analog switches=1.8V).
reference=0.0V/1.8V, analog=1.1V, digital=1.8V
4. What is the power dissipation breakdown of your device (e.g. total=12mW: references=2mW, analog=5mW, digital=3mW,
calibration=2mW)? Please be clear about on-chip or off-chip voltage references, and provide power in either case.
total power = 203.5uW, external reference = 26.5uW, analog = 72.6uW, digital = 104.4uW
5. If any calibration is applied, please identify whether it is on-chip or off-chip.
No calibration is applied.

Undecided

N/A
A 0.0375mm2 203.5µW 108.8dB DR DT Single-Loop DSM Audio ADC Using a Single-Ended Ring

Amplifier Based Integrator in 180nm CMOS

[Placeholder for Author List]

[Placeholder for Affiliations]

Demands for battery-powered consumer electronics have driven the evolution of power-efficient high-

resolution low-bandwidth ADCs. Small area and low power are both critical for these applications due to

increasing battery life and shrinking form-factors. Flicker noise poses an issue for such systems although

the use of well-known techniques in state-of-the-art designs such as chopper stabilization [1-2] are often

sufficient for its mitigation. Alternatively, the pseudo-pseudo-differential architecture (PPD) [3] has

demonstrated flicker cancellation through the use of single-ended circuits although area and power savings

promised by this technique remains undemonstrated. This paper presents a DT single-loop DSM audio

ADC utilizing a single-ended ring amplifier based integrator to achieve 108.8dB DR with 203.5µW power

consumption within a compact area of 0.0375mm2. The use of PPD with a merged adder contribute to this

work’s state-of-the-art power and area efficiency.

The PPD technique is a two-phase switched capacitor operation which processes differential signal in two

successive sampling operations (Fig. 1). As charge from the positive and negative input capacitors C 1+ and

C1- is transferred to the feedback capacitors C 2+ and C2-, single-ended op-amp noise is double-sampled.

Simultaneously the output capacitor, CPPD, samples the integrator output during positive integration (Phi1)

and is used serially in the next phase (Phi2) to produce a final output, Vout,PPD, which is the differentiated

value of the voltages stored on C2+ and C2-. The result is the summation of out-of-phase input signal and

suppression of in-phase input noise and op-amp noise. In other words, input signal is magnified by 6dB

while correlated noise is high-pass filtered according to the 1-z-1 transfer function. Uncorrelated noise sees

a 3dB increase in power. Area savings are achieved in the front-end integrator which is conventionally
sized for noise while power savings are gained in the back-end integrators through the elimination of the

differential half-circuitry.

The DT DSM is designed as a 3rd-order 3b single-loop feed-forward modulator and is clocked at a 5.8MHz

sample rate with an OSR of 145 (Fig. 2). Quantizer resolution is limited to 3b for minimization of area and

power overhead of the Dynamic Element Matching (DEM) circuitry. The input sampling capacitance is

chosen to be 7.3pF (8x915fF) and operates as the feedback-DAC of the modulator. This corresponds to a

kT/C SNR of 113dB with respect to a 1.8V reference. The second integrator uses minimum size 35fF MIM

capacitors while the back-end uses custom 5fF MOM unit capacitors. Due to the limited signal swing of the

multi-bit feed-forward architecture, the loop-filter operates on a reduced 1.1V supply without impacting the

dynamic range. Digital supply levels remain unchanged to drive the 1.8V reference switches. Because the

output of the loop-filter is differentiated, DC levels are not maintained in the modulator feedback and as a

result, pseudo-common-mode-feedback is provided locally around each PPD integrator using additional

switched-capacitor circuitry. Sizing of the pseudo-CMFB capacitors for ADC dynamic performance is not

strict and so capacitor values were selected based on optimal area and layout.

The 3b quantization is performed by a single-bit quantizer with the assistance of the merged adder. The

merged adder supplies three main functions: passive summation for the feed-forward modulator, SAR

feedback for the single-bit quantizer, and the differencing function of PPD. By incorporating the SAR

feedback DAC into the adder, a precise quantizer gain can be set from the ratioing of capacitors. This also

allows the SAR quantizer to begin conversion in advance during integrator settling and relaxes the digital

timing requirement of the single-loop modulator. PPD differentiation is accomplished simply by the omission

of traditional charge transfer switches. The feed-forward capacitors are directly coupled to the output of the

integrators and each period the capacitors re-sample the outputs of the integrators during Phi1 followed by

differentiation during the Phi2 phase. The output of the merged adder is quantized by a fully dynamic

comparator without fixed pre-amplification. The SAR logic and DEM operate fully asynchronously until the
end of the Phi2 phase where the digital outputs and DAC feedback controls are re-latched. DEM is

implemented using a standard Data-Weighted-Averaging algorithm. Traditional bootstrapping is employed

to linearize input sampling with a 1.65pF boost cap.

The first integrator is implemented as a single-ended ring amplifier (Fig. 3) to provide improved noise

performance over traditional fixed-bandwidth amplifiers [4]. The fast coarse estimation of the ring amplifier

is also utilized for the advance timing of the SAR conversion. The remaining integrators are implemented

with simple inverters owing to the small capacitances of the modulator back-end. The ring amplifier is

stabilized using a complimentary MOS pair at the output of stage-2 to form RDegen. The stabilizing effects of

RDegen are threefold: First, the reduction of RDegen provides additional ac phase margin at the expense of

ring amplifier gain-bandwidth product, a marginal drawback due to the dynamic behavior and cascoded

output stage of the ring amplifier. Simultaneously the stage-2 non-dominant pole, pSTG2, is moved out-of-

band. Finally, the stage-2 can be sized down due to its extended bandwidth and moves the stage-1 non-

dominant pole out-of-band. Due to noise/power requirements of stage-1, the non-dominant pole of stage-1

is naturally placed far out-of-band and the inclusion of additional gain stages 2 and 3 do not compromise

power for stability. First-order process tracking is enabled by the implementation of R Degen as a CMOS pair

which is sized to match stage-3. As the placement of the ring amplifier’s dominant pole is dependent on

stage-3 device threshold voltage, the implementation of R Degen as a matching CMOS pair compensates for

process changes. A dynamic slew assist is provided from the output of stage-1 and bypasses the effects of

RDegen and gate delay of the second stage. The slew-assist is implemented using a Native NMOS device

and draws zero quiescent power when the ring amplifier reaches linear settling. This allows the amplifier to

be independently optimized for large-signal slew and steady-state bandwidth similar to [4]. Ring amplifier

steady-state bandwidth is intentionally kept low to filter its own stage-1 noise providing further area and

power savings when compared with fixed-bandwidth amplifiers. The dynamic slew assist is not duplicated

for the ground-side of the ring amplifier output stage due to improved NMOS mobility and threshold voltage.
The ADC is implemented in a 180nm CMOS process and occupies an active area of 0.0375mm2. The ADC

is clocked at 5.8MHz with an OSR of 145 for a signal bandwidth of 20kHz. Single-tone and dual-tone output

spectrums are provided in Fig. 4. SNDR vs Amplitude measurements along with power consumption

breakdown and corner measurements are provided in Fig. 5. Accounting for the 1.2dB DR loss for

maximum-stable-amplitude, the ADC is thermal noise limited with half of the noise budgeted for kT/C input

sampling and the remaining within the loop-filter. A total of 72.6µW of measured power is supplied from the

1.1V analog supply. Of this total, 80% (58µW) is estimated by simulation to be dissipated by the ring

amplifier’s stage-1. The remaining power is consumed evenly between the ring amplifier’s stage-2 and

stage-3 in addition to the second and third integrators. Digital power totaling 104.4µW is provided from a

1.8V supply and is allocated towards the SAR logic, clock generation, input bootstrap, DEM, and reference

switch drivers. With the digital power comprising over half the total power consumption, significant scaling

benefits are expected in finer CMOS geometries. Off-chip low-noise op-amps provide 26.5µW from a 1.8V

reference which is shared between the input DAC and SAR DAC. The performance of the ADC is

summarized and compared with other state-of-the-art oversampling audio ADCs in Fig. 6. Compared to

Eland, which is implemented in a similar technology, the power is less than half with an area savings of

over 7x. This design achieves the highest FoM and lowest chip area. A die photo is shown in Fig. 7.

References:

[1] C. Lo et al., “A 116µW 104.4dB-DR 100.6dB-SNDR CT ΔΣ Audio ADC Using Tri-Level Current-
Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter,” International
Solid-State Circuits Conference (ISSCC), pp. 164-165, Feb. 2021.
[2] S. Mondal et al., “A 139µW 104.8dB-DR 24kHz-BW CTΔΣM with Chopped AC-Coupled OTA-Stacking
and FIR DACs,” International Solid-State Circuits Conference (ISSCC), pp. 166-167, Feb. 2021.
[3] C.Y. Lee et al., “A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz Bandwidth Using
Ring Amplifier Based Integrators,” IEEE Transactions on Circuits and Systems II: Express Briefs
(TCAS II), vol. 68, pp. 2327-2331, Jul. 2021.
[4] A. ElShater et al., “A 10mW 16b 15MS/s Two-Step SAR ADC With 95dB DR Using Dual-Deadzone
Ring Amplifier,” International Solid-State Circuits Conference (ISSCC), pp. 70-71, Feb. 2019.
References
(1) C. Lo et al., “A 116µW 104.4dB-DR 100.6dB-SNDR CT ΔΣ Audio ADC Using Tri-Level
Current-Steering DAC with Gate-Leakage Compensated Off-Transistor-Based Bias Noise Filter,”
International Solid-State Circuits Conference (ISSCC), pp. 164-165, Feb. 2021.
(2) S. Mondal et al., “A 139µW 104.8dB-DR 24kHz-BW CTΔΣM with Chopped AC-Coupled OTA-
Stacking and FIR DACs,” International Solid-State Circuits Conference (ISSCC), pp. 166-167,
Feb. 2021.
(3) C.Y. Lee et al., “A Pseudo-Pseudo-Differential ADC Achieving 105dB SNDR in 10kHz
Bandwidth Using Ring Amplifier Based Integrators,” IEEE Transactions on Circuits and Systems II:
Express Briefs (TCAS II), vol. 68, pp. 2327-2331, Jul. 2021.
(4) A. ElShater et al., “A 10mW 16b 15MS/s Two-Step SAR ADC With 95dB DR Using Dual-
Deadzone Ring Amplifier,” International Solid-State Circuits Conference (ISSCC), pp. 70-71, Feb.
2019.
 Charge Transfer
ɸ2 → ɸ1 C1+ → C2+
ɸ2 C1+ ɸ1 ɸ1 C2+ PPD Sample
V+ VC,PPD → VC,2+
ɸ1 ɸ2
vi2 CPPD Vout,PPD
VCM -A
Δf ɸ1
ɸ2 ɸ1
V- VCM
ɸ1 C1- ɸ2 ɸ2 C2-
Vout,PPD,input = V+ - V-(z-1)
ɸ2 C1+ ɸ1 ɸ1 C2+ v2out,PPD,OTA noise = v2out,OTA (1-z-1)
V+
ɸ1 ɸ2
vi2 CPPD Vout,PPD
VCM -A
Δf ɸ1
ɸ2 ɸ 1
V- VCMPPD Subtraction
ɸ1 C1- ɸ2 ɸ2 C2- Vout,PPD → VC,2- - VC,2+
Charge Transfer
ɸ1 → ɸ2 C1- → C2-

Fig. 1: Summary of pseudo-pseudo-differential (PPD) two-phase operation.

 CMFB 25fF
ɸ2 ɸ1 ɸ1 ɸ2 ɸ2 ɸ1
VCM VCM VCM VINP ɸ1 20fF
105fF 35fF 5fF ɸ2 VCM
ɸ1 ɸ 2 ɸ2 ɸ1 ɸ1 ɸ2 VCM SAR DAC + ɸ1
VINP ɸ2 7.3pF ɸ1 ɸ1 35fF ɸ2 ɸ2 10fF ɸ1 5fF Merged Adder
ɸ1 ɸ2e 7.3pF ɸ2 ɸ1 35fF ɸ1 ɸ2 20fF 5fF 5fF 10fF
DDWA[6:0]
DDWA[6:0] VCM -A VCM -A VCM -A VCM B1 B2
ɸ2 ɸ1e ɸ1 ɸ2 ɸ2 ɸ1 5fF 5fF 10fF
ɸ2 7.3pF ɸ1 35fF ɸ2 20fF 20fF
VCM
VINN ɸ1 7.3pF ɸ2 ɸ1 ɸ2 35fF ɸ1 ɸ2 ɸ1 10fF ɸ2 ɸ1 ɸ1
105fF 35fF 5fF SARFB VCM
ɸ1 20fF
ɸ1 ɸ2 ɸ2 ɸ1 ɸ1 ɸ2 VINN Asynchronous
VCM VCM VCM ɸ2 SAR Logic +
CMFB VCM D
Dynamic Element OUT[2:0]
10fF DDWA[6:0]
Matching

φ1 φ2 φ1 φ2 φ1
ɸ1e ɸ2e ɸ1e ɸ2e ɸ1e
Reset /Sample D2 D0 Reset /Sample D2 D0 Reset /Sample
Adder Output
D1 D1
PPD Subtraction

SAR Convert
tdly tdly
D[2:0] D[2:0]

DEM

Fig. 2: The proposed 145x OSR 3b 3rd Order DT-DSM PPD ADC with Merged Adder.
 P-Side Slew-Assist NMOSNVT Sized for Large-Signal Slew
(Not affected by RDegen)
VDZN Sized for Steady-State Bandwidth
PMOSLVT
VIN VDZCM VOUT Devices are High-Threshold
unless indicated otherwise
NMOSNVT LVT = Low-Threshold
NVT = Native Device
VDZP
RDegen
RDegen Reduction for
pSTG3
Gain-BW Steady-State Stability
pSTG3
Reduction
pSTG2 Phase-Margin
Gain (dB)

Improvement

pSTG2 f (Hz)
Fig. 3: Implementation of the first stage single-ended ring amplifier based integrator.
 -2dBFS
106.2dB SNR -7.5dBFS f1 = 19kHz
105.4dB SNDR f2 = 20kHz

20kHz
Bandwidth

IM3: -130.6dB, -128.4dB

IM2

262k FFT Points 262k FFT Points

IM4,6,8,10
32x Averaging 32x Averaging

Fig. 4: Measured ADC output spectrum at Fs=5.8MHz with single and dual-tone inputs.
 108.8dB Dynamic Range
MSA=-1.2dBFS
SNR
SNDR
FS=5.8MHz
FIN=3kHz
FBW=20kHz

DAC
REF=1.8V
26.5µW Analog
13% VDD=1.1V
Digital 72.6µW OSR = 145
VDD=1.8V 36% S1 S1
104.4µW S2 S2
51% S3 S3

Total Power: 203.5µW

Fig. 5: Measured dynamic range, power consumption, SNDR vs analog supply and SNDR vs Fs for three
random samples.
 Lo Mondal Eland Jang
This Work
ISSCC ‘21 ISSCC ‘21 VLSI ’20 ISSCC ‘20
Technology [nm] 180 28 65 160 65
Supply [V] 1.8/1.1 1.8/1.0 1.2 1.8 1.2
Area [mm2] 0.0375 0.07 0.39 0.27 0.28

DT PPD CT Tri-Level + CT FIR DAC DT Zoom CT Neg-R

Architecture
Csamp=7.3pF GLCOT IDAC + OTA Stack Csamp=13.6pF + FIR DAC

Sample Rate [MHz] 5.8 6.144 7.2 3.5 8

Bandwidth [kHz] 20 24 24 20 24
Power [μW] 203.5 116 139 440 134
Peak SNR [dB] 106.7 — 102.0 107.5 101.0
Peak SNDR [dB] 105.4 100.6 100.9 106.5 94.4
Dynamic Range [dB] 108.8 104.4 104.8 109.8 103.5
FoMSNDR [dB] 185.3 183.7 183.3 183.1 181.9
FoMDR [dB] 188.7 187.5 187.2 186.4 186.0
FoMSNDR = SNDR + 10log10(Bandwidth) – 10log10(Power)
FoMDR = Dynamic Range + 10log10(Bandwidth) – 10log10(Power)
Fig. 6: Performance summary of the PPD ADC and comparison to the state-of-the-art.
 Clock
Loop-Filter + Gen.

Input Bootstrap

150µm
Merged Adder
DWA
SAR
Logic

INT1 FB Cap Input Cap/DAC

250µm
Fig. 7: ADC chip micrograph with active area of 0.0375mm 2.
 APx500 Measurement Software
Signal Source Ext Clock
APx515 SI5342
Digilent Waveforms
+ MATLAB +/- 5V PSU
Bias Board
+ DUT
Logic Analyzer
Digilent Digital
Discovery

10µF
Electrolytic 2 11.6MHz SiLabs
- + Clock SI5342
Audio Precision +Eval
APx515 1k 1nF 2.4nF Analog PPD
ADI Board
VINCM Chip
4899 FS = 5.8MHz
Rout = 00 Digilent
Balanced Mode Digital
DOUT[2:0] Discovery

Signal Source Filter High-Frequency Drives Filters Driver

ac Coupling Signal Source Noise ADC Noise

Fig. S1: Chip measurement setup and circuit schematic of off-chip ADC input network.
 -7.5dBFS f1 = 79kHz
f2 = 80kHz

262k FFT Points

IM4,6,8,10 32x Averaging

Fig. S2: Measured ADC output spectrum at Fs=5.8MHz with out-of-band dual-tone input demonstrating
tolerance of input sampling timing mismatch of 1-z-1. An 80kHz signal is chosen due to the limitations of the
signal generator.