Hardware Questions

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1. Implement the hardware circuit for a 4-bit right shift register. Draw the block diagram
and write the truth table of the 4-bit right shift register.
2. Implement the hardware circuit for a 2:4 decoder using basic logic gates. Draw the block
diagram and write the truth table of the 2:4 decoder.
3. Implement the hardware circuit for a 4-bit BCD adder. Write the truth table of the 4-bit
BCD adder.
4. Implement the hardware circuit for a Binary to gray code converter using logic gates.
5. Implement the hardware circuit for a 4:1 MUX with proper logic gates.
6. Implement the hardware circuit for 1-bit magnitude comparator using basic logic gates.
Draw the block diagram and the truth table of the 1-bit magnitude comparator.
7. Implement the hardware circuit for 8:3 priority encoder using basic logic gates.
8. Implement the hardware circuit for the 8-bit parallel adder circuit using proper ICs for
4-bit full adder to perform binary addition of A: 1101 1000 and B: 1000 1101.
9. Implement a full subtractor using basic logic gates. Draw the block diagram and write the
truth table of the full subtractor.
10. Implement the hardware circuit for a gray to binary converter using logic gates.
11. Implement the hardware circuit for a full adder using logic gates. Draw the block diagram
and the truth table of the full adder.
12. Simulate the 4-bit parallel adder circuit for performing binary addition between A: 1011
and B: 1111 using 4-bit parallel adder IC.
13. Simulate the adder / subtractor unit using XOR gates and IC for 4-bit parallel adder for
performing binary addition and subtraction between A: 1101 and B: 1011.
14. Simulate the hardware circuit for a 1:4 Demultiplexer using logic gates. Draw the block
diagram and write the truth table of the Demultiplexer.
15. Implement the hardware circuit for a 4-bit left shift register. Draw the block diagram and
write the truth table of the 4-bit left shift register.
16. Implement the hardware circuit for a 4:2 encoder using logic gates. Draw the block
diagram and write the truth table of the 4:2 encoder.
17. Simulate the adder / subtractor unit using XOR gates and IC for 4-bit parallel adder for
performing binary addition and subtraction between A: 1001 and B: 0011.
18. Implement the hardware circuit for the 8-bit parallel adder circuit using proper ICs for
4-bit full adder.
19. Implement 4-bit Serial Adder using D-flip flop and use 4-bit shift registers for inputs.
20. Implement 4-bit full subtractor using a 4-bit parallel adder IC 7483 and XOR gate.
Software (VHDL) Questions:
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1. Write a VHDL program for implementing a 8:3 Encoder using behavioural modelling.
Draw the block diagram and write the truth table of the 8:3 Encoder.
2. Write a VHDL program for implementing a 1:8 demultiplexer using Case statement.
Draw the block diagram and write the truth table of the 1:8 demultiplexer.
3. Write a VHDL program for implementing a full subtractor. Draw the block diagram and
the truth table of the full subtractor.
4. Write a VHDL program for implementing a 3:8 decoder using behavioural modelling.
5. Write a VHDL program for implementing a 4-bit magnitude comparator. Draw the block
diagram and write the truth table of the 4-bit magnitude comparator.
6. Write a VHDL program for implementing the following POS expression using data flow
modelling:
(~a v~ b) ^ (~a v c) ^ (b v c)
7. Write a VHDL program for implementing a 8:1 multiplexer using if-else statements.
Draw the block diagram and the truth table of the 8:1 multiplexer.
8. Write a VHDL program for implementing a 4:2 priority encoder. Draw the block diagram
and the truth table of the 4:2 priority encoder.
9. Write a VHDL program for implementing for a full adder using data flow modelling.
Draw the block diagram and the truth table of the full adder.
10. Write a VHDL program for implementing a 4:2 priority encoder using if-else statements.
Draw the block diagram and the truth table of the 4:2 priority encoder.
11. Write a VHDL program for implementing a 4:1 multiplexer using the case statement.
Draw the block diagram and the truth table of the 4:1 multiplexer.
12. Write a VHDL program to implement 8:3 encoder using data flow modelling. Draw the
block diagram and write the truth table of the 8:3 Encoder.
13. Write a VHDL program for implementing a full adder using the CASE statement. Draw
the block diagram and the truth table of the full adder.
14. Write a VHDL program for implementing a full subtractor using the CASE statement.
Draw the block diagram and the truth table of the full subtractor.
15. Write a VHDL program for implementing the following SOP expression using data flow
modelling:
(a ^ b) v (b ^ ~c) v (c ^ ~a)
16. Write a VHDL program for implementing a 4-bit priority encoder using Case statement.
Draw the block diagram and the truth table of the 4:2 priority encoder.
17. Write a VHDL program for implementing a 8:1 multiplexer using data flow modelling.
Draw the block diagram and the truth table of the 8:1 multiplexer.
18. Write a VHDL program for implementing a 1:4 demultiplexer using if-else statements.
Draw the block diagram and write the truth table of the 1:4 demultiplexer.
19. Write a VHDL program for implementing half subtractor using data flow modelling.
Draw the block diagram and the truth table of the half subtractor.
20. Write a VHDL program for implementing the following SOP expression using data flow
modelling:

(x ^ y) v (~x ^~ z) v (y ^ ~z)