Implement a Verilog model and display the output for a set of sample data together with

the wave form obtained for the problems given below

1. Design a 4-Bit Carry Look-Ahead Adder
2. Design a sequential traffic light controller for the intersection of street A and street B. Each
street has traffic sensors, which detect the presence of vehicles approaching or stopped at
the intersection. Sa = ‘1’ means a vehicle is approaching on street A, and S b = ‘1’ means a
vehicle is approaching on street B. Street A is a main street and has a green light until a car
approaches on B. Then the lights change, and B has a green light. At the end of 50 seconds,
the lights change back unless there is a car on street B and none on A, in which case the B
cycle is extended for 10 additional seconds. If cars continue to arrive on street B and no car
appears on street A, B continues to have a green light. When A is green, it remains green
at least 60 seconds, and then the lights change only when a car approaches on B. Figure 4-
13 shows the external connections to the controller. Three of the outputs (Ga, Ya, and Ra)
drive the green, yellow, and red lights on street A. The other three (Gb, Yb, and Rb) drive
the corresponding lights on street B.
3. Design a simple scoreboard, which can display scores from 0 to 99 (decimal). The input to
the system should consist of a reset signal and control signals to increment or decrement
the score. The two-digit decimal count gets incremented by 1 if increment signal is true and
is decremented by 1 if decrement signal is true. If increment and decrement are true
simultaneously, no action happens.
The current count is displayed on seven-segment displays. In order to prevent accidental
erasure, the reset button must be pressed for five consecutive cycles in order to erase the
scoreboard. The scoreboard should allow down counts to correct a mistake (in case of
accidentally incrementing more than required).
4. Design a multiplier for unsigned binary numbers. When we form the product A * B, the
first operand (A) is called the multiplicand, and the second operand (B) is called the
multiplier. Binary multiplication requires only shifting and adding.
5. Design a scanner for a keypad with three columns and four rows. The keypad is wired in
matrix form with a switch at the intersection of each row and column. Pressing a key
establishes a connection between a row and column. The purpose of the scanner is to
determine which key has been pressed and output a binary number N = N3N2N1N0, which
corresponds to the key number. For example, pressing key 5 must output 0101, pressing
the * key must output 1010, and pressing the # key must output 1011.When a valid key has
been detected, the scanner should output a signal V for one clock time. Assume that only
one key is pressed at a time. The design must include hardware to protect the circuitry from
malfunction due to keypad bounces.
6. Design a parallel divider for positive binary numbers. Design a circuit to divide an 8-bit
dividend by a 4-bit divisor to obtain a 4-bit quotient. Just as binary multiplication can be
carried out as a series of add and shift operations, division can be carried out by a series of
subtract and shift operations.

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7. A controller to control the traffic light in five-way intersection
8. Construct a full adder from two 4x1 multiplexers. One multiplexer is to generate the sum,
and the other generates the carryout. Write a dataflow description (in Verilog) of the full
adder. Use a 5-ns delay for any gate including XOR. Draw the truth table of this adder and
derive the Boolean function after minimization. Simulate and verify the circuit.
9. Write a data-flow description (in Verilog) of a system that has three one-bit inputs, a(1),
a(2), and a(3), and one one-bit output b. The least significant bit is a(1). The output b is 1
only when {a(1)a(2)a(3)} = 1, 2, 4, or 7 (all in decimal); otherwise, b is 0. Derive a
minimized Boolean function of the system and write the data-flow description. Simulate
the system and verify that it works as designed. What is the function of this system?
10. Describe a system that divides D/V to give a quotient, Q, and Remainder,R. The dividend,
D, is three bits; the divisor, V, is two bits. If V = 0, set a flag Z to 1. Write the truth table
of the system and obtain the Boolean functions of Q, R, and Z. Use VHDL and Verilog to
describe the system.
11. Design a multiplier to multiply X * Y where X is three bits and Y is two bits. Find the
Boolean function of the output and describe the system using VHDL and Verilog.
12. Add asynchronous clear signal to the JK flip-flop. Write Verilog to describe the flip-flop
and simulate the code.
13. Use binary-to-integer conversion to describe a four-bit even counter with active low clear
and synchronous load (load from external P to Q). Use Verilog, simulate, and verify.
14. Design a four-bit parity generator. The output is 0 for even parity and 1
for odd parity. Write Verilog codes.
15. Design a counter that counts 0, 1, 3, 6, 7, 0, 1… using the state-machine approach. Show
all details of your answer. Write Verilog codes.
16. Construct a two-digit decade counter that counts from 0 to 99. Write Verilog codes.
17. Write Verilog code for the universal shift register.
18. Write a Verilog code for a 2 X 1 Multiplexer using Verilog Conditional (?) operator.
19. Write the Verilog code describing the full subtractor.
20. Write the Verilog Code for a Three-Bit Binary Counter Using the case Statement
21. Write a Verilog code of a priority encoder.
22. Write a Verilog code for the state diagram given below

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23.

24.

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25.

26. Write Verilog code for 2x1 multiplexer with active low enable.
27. Write Verilog Code for a 2x2 Unsigned Combinational Array Multiplier.
28. Write Verilog Code for a two-bit magnitude comparator
29. Write Verilog Code three-bit ripple-carry adder
30. Write Verilog Code a three-bit carry-lookahead adder
31. Write Verilog code for a combinational circuit with three inputs and one output.
(a) The output is 1 when the binary value of the inputs is less than 3. The output is 0
otherwise.
(b) The output is 1 when the binary value of the inputs is an even number.
32. Using a case statement, write and verify a Verilog model of the circuit that converts a four-
bit Gray code to a bit four binary number.
33. Using a case statement, write and verify a Verilog model of the circuit that converts a 8, 4,
–2, –1 code to BCD
34. Using a case statement, write and verify a Verilog model of the circuit that converts a 8,
4, –2, –1 code to Gray code
35. Using four half-adders design and implement using Verilog a full-subtractor circuit
incrementor. (A circuit that adds one to a four-bit binary number.)
36. Using four half-adders design and implement using Verilog a combinational decrementor.
(A circuit that subtracts one from a four-bit binary number.)
37. Write the HDL dataflow description of a quadruple 2-to-1-line multiplexer with enable
38. Implement a Verilog code for a full adder with two 4 x 1 multiplexers.
39. Implement a Verilog code for the following Boolean function with a multiplexer F(A, B,
C, D) = Σ(0, 2, 5, 8, 10, 14)
40. Implement a Verilog code for the following Boolean function with a multiplexer F(A, B,
C, D) = ∏(2,6,11)
41. Implement a Verilog code for a 16 x 1 multiplexer with two 8 x 1 and one 2 x 1 multiplexers
42. Write and verify a Verilog behavioral model of a four-bit counter that counts in the
sequence 0, 1, . . . , 9, 0, 1, 2, . . . .

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43. Write and verify a Verilog structural model of a three-bit counter that counts in the
sequence 0, 2, 4, 6, 0, . . . .
44. Write and verify a Verilog behavioural model of a three-bit counter that counts in the
sequence 0, 2, 4, 6, 0, . . . .
45. Write and verify a Verilog behavioural model of for a Mealy state machine that detects a
sequence of three or more consecutive 1's in a string of bits coming through an input line.
46. A synchronous Moore machine has two inputs, x1, and x2, and output y-out . If both inputs
have the same value the output is asserted for one cycle; otherwise the output is 0. Develop
a state diagram and a write a Verilog behavioral model of the machine.
47. A synchronous Moore machine has two inputs, x1, and x2, and output y-out . If both
inputs have different value the output is asserted for one cycle; otherwise the output is 0.
Develop a state diagram and a write a Verilog behavioral model of the machine.
48. Draw a state diagram and write a Verilog model of a Mealy synchronous state machine
having a single input, x_in, and a single output y_out, such that y_out is asserted if the total
number of 1’s received is a multiple of 3.
49. Write a Verilog model of a synchronous finite state machine whose output is the sequence
0, 2, 4, 6, 8 10, 12, 14, 0 . . . . The machine is controlled by a single input, Run, so that
counting occurs while Run is asserted, suspends while Run is de-asserted, and resumes the
count when Run is re-asserted. Clearly state any assumptions that you make.
50. Write Verilog code for the modified 4 bit register that has a parallel load capability and a
synchronous clear capability. The register is cleared synchronously when the clock goes
through a positive transition and the clear input is equal to 1.
51. Write Verilog code for a four‐bit binary ripple countdown counter using flip‐flops that
trigger on the positive‐edge of the clock
52. Write Verilog code for a four‐bit binary ripple countdown counter using flip‐flops that
trigger on the negative‐edge of the clock
53. Write Verilog code for a BCD ripple counter that can be constructed using a four‐bit binary
ripple counter with asynchronous clear and a NAND gate that detects the occurrence of
count 1010.
54. Write Verilog code for a counter with T flip‐flops that goes through the following binary
repeated sequence: 0, 1, 3, 7, 6, 4.
55. Write Verilog code for a counter with T flip‐flops that goes through the following binary
repeated sequence: 0, 1, 4, 7, 6, 3.
56. Write and verify the HDL behavioural descriptions of the four‐bit register
57. Write and verify the HDL structural descriptions of the four‐bit register
58. Write and verify an HDL behavioural description of a four‐bit register with parallel load
and asynchronous clear.
59. Write and verify the HDL structural description of the four‐bit register with parallel load.
Use a 2 * 1 multiplexer for the flip‐flop inputs. Include an asynchronous clear input.
60. Write and verify the HDL behavioural descriptions of the four‐bit up–down counter
61. Write and verify the HDL structural descriptions of the four‐bit up–down counter
62. Write and verify the HDL behavioural description of a four‐bit up–down counter with
parallel load using the following control inputs:
The counter has three control inputs for the three operations: Up, Down, and Load. The
order of precedence is: Load, Up, and Down.

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63. Write and verify the HDL behavioural description of a four‐bit up–down counter with
parallel load using the following control inputs: The counter has two selection inputs to
specify four operations: Load, Up, Down, and no change.
64. Write Verilog code to develop a Mealy machine that will detect the pattern 00102 in a serial
bit stream, with the LSB arriving first.
65. Write Verilog code to develop a Moore machine that will detect the pattern 01102 in a
serial bit stream, with the LSB arriving first.
66. Write Verilog code to develop 4 bit serial shift register.
67. Write Verilog code to develop a behavioural model of a 3 to 8 decoder.
68. Write Verilog code for a serial adder
69. Write Verilog code for 4 bit shift left register
70. Write Verilog code for 4 bit circular shift left register
71. Write Verilog code for BCD ripple counter
72. Write Verilog code for 4 bit UP Down counter with count enable input
73. Write Verilog code for 4 bit ring counter

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