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Demultiplexers
BY UNSA SHAKIR
Exercise:
MUX Types
2-to-1 (1 select line)
4-to-1 (2 select lines)
8-to-1 (3 select lines)
16-to-1 (4 select lines)
Multiplexers
A multiplexer has
N control / select inputs
2N data inputs
1 output
Figure : Logic diagram of 2x1 mux Figure : Schematic symbol of 2x1 mux
S Z
0 I0
1 I1
4-to-1 Multiplexer (MUX)
I0
I1
MUX
O
I2
I3
S1 S0
S1 S0 O
0 0 I0
0 1 I1
1 0 I2
1 1 I3
8 : 1 Multiplexer
S0 S1 S3 Z
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7
8 : 1 Multiplexer
Multiplexer (Bus)
Exercise:
Exercise:
1 0 A B C F
0 1 0 0 0 1 C 0
1 2
C F
F 0 0 1 0 C 1 4:1
0 3 0
8:1 0 1 0 1 2 MUX
0 4 C 1
0 5
MUX 0 1 1 0 3
S1 S0
1 6 1 0 0 0
0 A B
1 7 S2 S1 S0 1 0 1 0
1 1 0 1
A B C 1
1 1 1 1
"Lookup Table"
Multiplexers
• Efficient implementation:
Implementation Of Logic Functions
using Multiplexer
f(a, b, c) = a’b’c + ab
0 0
A B C F 1 1
0 0 0 0 0 2
0 0 1 1 0 3 8:1 MUX
0 1 0 0 F
0 4
0 1 1 0 0 5
1 0 0 0 1 6
1 0 1 0 1 7
1 1 0 1
1 1 1 1 S2 S1 S0
A B C
f(a, b, c) = a’b’c + ab
A B C O F
0 0 0 0 C 0
C
0 0 1 1 0 1 4:1 MUX
0 1 0 0 0 2 F
0
0 1 1 0 1 3
1 0 0 0
0
1 0 1 0
1 1 0 1
1 S1 S0
1 1 1 1
B C
f(a, b, c) = F= A’B’C’D + A’B’CD + A’BC’D’ + AB’CD
+ ABC’D’ + ABC’D + ABCD’ +ABCD
A B C D O F
0 0 0 0 0
D
0 0 0 1 1
D 0
0 0 1 0 0
D
0 0 1 1 1 1
0 1 0 0 1 D’ 2
D’
0 1 0 1 0
0 1 1 0 0
0 3 8:1 MUX
0 F
0 1 1 1 0 4
1 0 0 0 0
0 5
1 0 0 1 0
1 0 1 0 0 1 6
D’
1 0 1 1 1 7
1 1 0 0 1
1
1 1 0 1 1
S2 S1 S0
1 1 1 0 1
1 A B C
1 1 1 1 1
Example
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Example
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
4-1 Multiplexer (SOP circuit)
f = s1 s 0 w 0 + s 1 s 0 w 1 + s 1 s 0 w 2 + s 1 s 0 w 3
Example
• Multiple functions of A, B, C
full decoder as for memory address
– F1 = A B C bits stored in memory
A B C
– F2 = A + B + C
– F3 = A' B' C' A'B'C'
– F4 = A' + B' + C' A'B'C
– F5 = A xor B xor C A'BC'
– F6 = A xnor B xnor C A'BC
AB'C'
A B C F1 F2 F3 F4 F5 F6
0 0 0 0 0 1 1 0 0 AB'C
0 0 1 0 1 0 1 1 1
ABC'
0 1 0 0 1 0 1 1 1
0 1 1 0 1 0 1 0 0 ABC
1 0 0 0 1 0 1 1 1
1 0 1 0 1 0 1 0 0
1 1 0 0 1 0 1 0 0
1 1 1 1 1 0 0 1 1 F1 F2 F3 F4 F5
F6
Truth Table for a 2-1 Multiplexer
Let’s Derive the SOP form
s x1 x 2
s x1 x2
s x1 x 2
s x1 x2
f x1 0
f
s x2 1
x2
A B
A B W X Y Z
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I
1 : 2 Demultiplexer
S0 Y0 Y1
0 D 0
1 0 D
1-to-4 De-Multiplexer (DEMUX)
D0
DEMUX
D1
X
D2
D3
B A
B A D0 D1 D2 D3
0 0 X 0 0 0
0 1 0 X 0 0
1 0 0 0 X 0
1 1 0 0 0 X
1 : 8 Demultiplexer
1 : 8 Demultiplexer (Truth Table)
S0 S1 S3 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 D 0 0 0 0 0 0 0
0 0 1 0 D 0 0 0 0 0 0
0 1 0 0 0 D 0 0 0 0 0
0 1 1 0 0 0 D 0 0 0 0
1 0 0 0 0 0 0 D 0 0 0
1 0 1 0 0 0 0 0 D 0 0
1 1 0 0 0 0 0 0 0 D 0
1 1 1 0 0 0 0 0 0 0 D
Demultiplexers as General-purpose
Logic
• F1 = A' B C' D + A' B' C D + A B C D
• F2 = A B C' D’ + A B C
0 A'B'C'D'
• F3 = (A' + B' + C' + D') 1 A'B'C'D
2 A'B'CD' F1
3 A'B'CD
4 A'BC'D'
5 A'BC'D
6 A'BCD'
4:16 7 A'BCD
Enable DEC 8 AB'C'D' F2
9 AB'C'D
10 AB'CD'
11 AB'CD
12 ABC'D'
13 ABC'D
14 ABCD'
15 ABCD F3
A B C D