Experiment No.

2
Introduction to Combinational Circuits
Group name: Group 7
Group leader: JOSE DOROSAN
Group Member:
 Joshua Bayrante
 Jose Dorosan
 Mark Kenchi Imperial
 Avene Carl Manzano
 Joy Peconcillo
 Rona Periabras
 Jonathan Sumayo

NAME: Joy B. Peconcillo | BSEE 3B

Introduction:

Combinational circuit is a circuit in which we combine the different gates in the circuit, for example
encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational circuits
are following:

• The output of combinational circuit at any instant of time, depends only on the levels present at
input terminals.
• The combinational circuit do not use any memory. The previous state of input does not have any
effect on the present state of the circuit.
• A combinational circuit can have an n number of inputs and m number of outputs.

Block Diagram of combinational circuit

Objectives:

1. To simulate the adder and subtractor circuits using basic gates and universal gates
2. To simulate various types of multiplexers and demultiplexers
3. To simulate decoders and encoders
Equipment:

Smart Phone with Logic Circuit Simulator Pro

Procedure:

1. Using at most 8 NOR and 4 AND gates, construct both half adder circuit.

Circuit:

Test the half adder for all possible inputs and fill the truth table below:

X Y C S
0 0 0 0

0 1 0 1
1 0 0 1
1 1 1 0
 2. Using at most 8 NOR and 4 AND gates, construct full adder circuit.

Circuit:

Test the full adder for all possible inputs and fill the truth table below:

X y z C S
0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1
3.Using at most 8 NOR and 4 AND gates, construct both half subtractor circuit.
Circuit:

Test the half subtractor for all possible inputs and fill the truth table below:

X Y
0 0
0 1
1 0
1 1
C S
0 0
1 1
1 0
0 0

4.Using at most 8 NOR and 4 AND gates, construct full subtractor circuit.
Test the full subtractor for all possible inputs and fill the truth table below:

X y z C S
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
5.Construct the following circuits using NAND Gates only
a. Half Adder
b. Full Adder

c. Half Subtractor

d. Full Subtractor
 6. Implement your own 2-to-1 MUX using Karnaugh map or Boolean algebra identities. You
should implement it using only NAND gates. (At most 4 NAND gates are allowed.)

Circuit:

Test the multiplexer for all possible inputs and fill the truth table below:

S A B Y

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1
1 1 1 1
7. Construct a 4:1 Multiplexer using NAND Gates only

Circuit:
Test the multiplexer for all possible inputs and fill the truth table below:
Enable Outpu
Select Inputs Inputs
Input t
S1 S0 E I0 I1 I2 I3 Y
X X 1 X X X X 1

0 0 0 0 X X X 0

0 0 0 1 X X X 0

0 1 0 X 0 X X 0

0 1 0 X 1 X X 0

1 0 0 X X 0 X 0

1 0 0 X X 1 X 0

1 1 0 X X X 0 0

1 1 0 X X X 1 0

8. Construct a 4:1 Demultiplexer using NAND Gates only

Circuit:
Test the demultiplexer for all possible inputs and fill the truth table below:
Enable Data
Select Inputs Out puts
Input Input
S1 S0 E D Y1 Y2 Y3 Y4
X X 0 0 0 0 0 0

0 0 1 1 1 0 0 0

0 1 1 1 0 1 0 0

1 0 1 1 0 0 1 0

1 1 1 1 0 0 0 1

9. Design and construct a 2-to-4 Decoder using AND and NOT

gates.

Circuit
 Fill the truth table of a 2-to-4 Decoder given below:

I1 I0 Y3 Y2 Y1 Y0
0 0 1 0 0 0

0 1 0 1 0 0

1 0 0 0 1 0

1 1 0 0 0 1

10. Design and construct a 4-to-2 Encoder using AND and NOT
gates. You may use Karnaugh maps. Don’t forget to take “don’t
care” conditions into consideration.
Circuit:
Fill the truth table of a 4-to-2 Encoder given below considering “don’t care” conditions.
Y3 Y2 Y1 Y0 I1 I0
0 0 0 0 X X

0 0 0 1 0 0

0 0 1 X 0 1

0 0 1 X 0 1

0 1 X X 1 0

0 1 X X 1 0

0 1 X X 1 0

0 1 X X 1 0

1 X X X 1 1

1 X X X 1 1

1 X X X 1 1

1 X X X 1 1

1 X X X 1 1

1 X X X 1 1

1 X X X 1 1

1 X X X 1 1