VERILOG ASSIGNMENT-1 (ECC-104):

Aman Tiwari
ENROLLMENT NO.:23116010 Sub-Batch:EC-1

Lin Syntax errors

e

1 module name must be Exmpl_3(A,B,C,D,F) using underscore instead of dash and line 1
must end with semicolon.

2 only inputs must be mentioned in form of boolean variables and outputD is not a
boolean variable , we can write it as A,B,C,D,F and the line 2 must end with a semicolon
not a comma.

3 once the port B is given as input it cannot be given as output to the module again,we
can change the ouput port of the module and also end the line 3 with a semi colon.

4 A cannot be a output of a gate if it is already given as overall input of the module.

5 in case of not gate there cannot be more than two inputs as in case of not gate there
can be only one input and one output only and line 5 must also terminate with
semicolon.

6 OR must be replaced by or as verilog is case sensitive language and F,B,C must be

written instead of using semicolon between B and C.

7 endmodule doesn’t need to be terminated with semicolon.

a)

b)

c)
a)

A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

b)The User defined primitive Code for the 4bit majority function is as follows
primitive 4_bit_majority(A,B,C,D,F); output F; input A,B,C,D; table

//The boolean expression for F will be sum(7,11,13,14,15) as sum of minterms

// A B C D : F

0 0 0 0 : 0;

0 0 0 1 : 0;

0 0 1 0 : 0;

0 0 1 1 : 0;

0 1 0 0 : 0;

0 1 0 1 : 0;

0 1 1 0 : 0;

0 1 1 1 : 1;

1 0 0 0 :0;
1 0 0 1 : 0;

1 0 1 0 : 0;

1 0 1 1 : 1;

1 1 0 0 : 0;

1 1 0 1 : 1;

1 1 1 0 : 1;

1 1 1 1 : 1;

endtable endprimitive
Explanations: This represents a user-defined combinational circuit, specified by the user.
Similar to system primitives or predefined gates such as AND, NOR, etc., when the name of
the primitive function mentioned above is invoked along with its port list, it will generate the
output based on the inputs as defined by the truth table within the code. This process is
commonly referred to as instantiation of the primitive circuit.
Q3.38

//Now write test bench to simulate the inputs given in the figure

module t_circuit_with_UDP_02467;

wire e,f; reg a,b,c,d; circuit_with_UDP_02467 uut (e,f,a,b,c,d); //

instantiate the module

initial #80 $finish; initial fork a=

1'b1; b = 1'b1; c = 1'b0; d = 1'b0;

#40 a = 1'b0;

#20 b = 1'b0;
 #40 b = 1'b1;

#60 b = 1'b0;

#10 c = 1'b1;

#20 c = 1'b0;

#30 c = 1'b1;

#40 c = 1'b0;

#50 c = 1'b1;

#60 c = 1'b0;

#70 c = 1'b1;

#15 d = 1'b1;

#30 d = 1'b0;

#50 d = 1'b1;

#70 d = 1'b0; join

endmodule

b) The simulation of test bench: