NITISH KUMAR 17/IEC/031

EXPERIMENT:13

AIM:-Write a VHDL code for 2 bit comparater .

SOFTWARE USED:- ModelSim .

THEORY:- The 2 bit comparater consists of Four input, three output to make selections. The input
bit A1,A0,B1.B0 is transmitted to output bits S(a<b), E(a=b) and G(a>b).

CIRCUIT DIAGRAM:-

TRUTH TABLE:-
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INPUT OUTPUT
A1 A0 B1 B0 S E G
0 0 0 0 0 1 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 0 1
0 1 0 1 0 1 0
0 1 1 0 1 0 0

0 1 1 1 1 0 0
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 1 0
1 0 1 1 1 0 0
1 1 0 0 0 0 1
1 0 1 0 0 1

PROGRAM CODE:-
program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bit2comp is
Port ( a1,a0,b1,b0: in STD_LOGIC ;
s,e,g: out STD_LOGIC );
end bit2comp;

architecture dataflow of bit2comp is

begin
s<= ((not a0) and b1 and b0) or ((not a1) and (not a0) and b0) or (b1 and (not a1) );
e<=(a1 xnor b1) and (a0 xnor b0);
g<=(a0 and (not b1) and (not b0)) or (a1 and a0 and (not b0)) or (a1 and (not b1) );
end dataflow;

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OUTPUT:-

RESULT:- The 2 bit comparater designe have been realized and simulated using VHDL codes.

17/IEC/031