NITISH KUMAR 17/IEC/031

, EXPERIMENT:9 ,
AIM:- Write VHDL codes for encoder 4-2.
SOFTWARE USED:- ModelSim .
THEORY:- Encoders, as the name suggest, encodes a larger bit of information into a smaller bit
value.An encoder is a device , circuit, transducer, software program, algorithum or person that converts
information from one format or code to another , for the purpose of standardization, speed, secrecy,
security, or saving space by shrinking size.

CIRCUIT DIAGRAM:-

Y0
Y1 Ao

Y2
A1
Y3

TRUTH TABLE:
INPUT OUTPUT
Y0 Y1 Y2 Y3 A0 A1
1 0 0 0 0 0
0 1 0 0 1 0
0 0 1 0 0 1
0 0 0 1 1 1

NITISH KUMAR 17/IEC/031

NITISH KUMAR 17/IEC/031

BOOLEAN EXPREASSION: A0= y1+y3

A1= y2 +y3
Program:
Library ieee;
use ieee. std_logic_1164.all;
entity encoder4_2 is
port(a,b,c,d:in std_logic;
en:in std_logic;
v0,v1:out std_logic);
end encoder4_2;
architecture data_flow of encoder4_2 is
begin
v0<=(b or d ) and en; v1<=(c or d) and en;
end data_flow;

output

RESULT:- The encoder 4-2 designed have been realized and simulated using VHDL codes.

NITISH KUMAR 17/IEC/031

NITISH KUMAR 17/IEC/031

, EXPERIMENT:10 ,
AIM:- Write VHDL codes for encoder 8-3.
SOFTWARE USED:- ModelSim .
THEORY:- Encoders, as the name suggest, encodes a larger bit of information into a smaller bit
value.An encoder is a device , circuit, transducer, software program, algorithum or person that converts
information from one format or code to another , for the purpose of standardization, speed, secrecy,
security, or saving space by shrinking size.

CIRCUIT DIAGRAM:-

NITISH KUMAR 17/IEC/031

NITISH KUMAR 17/IEC/031

TRUTH TABLE:
INPUT OUTPUT
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
X X X X X X X X 0 0 0

BOOLEAN EXPREASSION: A=D7+D5+D3+D1 B=D7+D6+D3+D2

C=D7=D6=D5+D4

program
Library ieee;
use ieee. std_logic_1164.all;
entity encoder8_3 is
port(i0,i1,i2,i3,i4,i5,i6,i7:in std_logic;
en:in std_logic;
v0,v1,v2:out std_logic);
end encoder8_3;
architecture data_flow of encoder8_3 is
begin
v0<=(i7 or i5 or i3 or i1)and en;
v1<=(i7 or i6 or i3 or i2) and en;
v2<=(i7 or i6 or i5 or i4)and en;
end data_flow;

NITISH KUMAR 17/IEC/031

NITISH KUMAR 17/IEC/031

output

RESULT:- The encoder 8-3 designed have been realized and simulated using VHDL
codes.

NITISH KUMAR 17/IEC/031

NITISH KUMAR 17/IEC/031

, EXPERIMENT:11 ,
AIM:- Write VHDL codes for decoder 2-4.
SOFTWARE USED:- ModelSim .
THEORY:- Decoders, as the name suggest, decodes a small bit of information into a larger bit value.
An Decoder is a device which does the reverse of an encoder , undoing the encoding so that the original
information can be retrieved. The same method used to encode is usually just reversed in order to decode.
CIRCUIT DIAGRAM:

TRUTH TABLE:
OUTPUT INPUT
Y0 Y1 Y2 Y3 X0 X1
1 0 0 0 0 0
0 1 0 0 1 0
0 0 1 0 0 1
0 0 0 1 1 1

BOOLEAN EXPREASSION: Y0=(NOT X0) AND (NOT X1) Y1=X0 AND (NOT X1)
Y2=(NOT X0)AND X1 Y2=X0 AND X1

program
Library ieee;
use ieee. std_logic_1164.all;

NITISH KUMAR 17/IEC/031

NITISH KUMAR 17/IEC/031

entity dec2_4 is
port(a,b,en :in std_logic;
y0,y1,y2,y3:out std_logic);
end dec2_4;
architecture data_flow of dec2_4 is
begin
y0<=(not a) and (not b)and en;
y1<=(not a) and b and en;
y2<=a and (not b)and en;
y3<=a and b and en;
end data_flow;

output

RESULT:- The decoder 2-4 designed have been realized and simulated using VHDL codes.

NITISH KUMAR 17/IEC/031

NITISH KUMAR 17/IEC/031

, EXPERIMENT:12 ,
AIM:- Write VHDL codes for decoder 3-8.
SOFTWARE USED:- ModelSim .
THEORY:- Decoders, as the name suggest, decodes a small bit of information into a larger bit value.
An Decoder is a device which does the reverse of an encoder , undoing the encoding so that the original
information can be retrieved. The same method used to encode is usually just reversed in order to decode.
CIRCUIT DIAGRAM:

NITISH KUMAR 17/IEC/031

NITISH KUMAR 17/IEC/031

TRUTH TABLE:
OUTPUT INPUT
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 X X X
BOOLEAN EXPREASSION: YO=(NOT A) AND (NOT B)AND (NOT C), Y1= (NOT A)AND(NOT B)AND C
Y2=(NOT A) AND B( NOT C), Y3=(NOT A)AND B AND C, Y4=A AND(NOT B) AND (NOT C)
Y5=A AND (NOT B) AND C, Y6=A AND B AND (NOT C), Y7=A AND B AND C.

Program
Library ieee;
use ieee. std_logic_1164.all;
entity dec3_8 is
port(a,b,c,en :in std_logic;
y0,y1,y2,y3,y4,y5,y6,y7:out std_logic);
end dec3_8;
architecture data_flow of dec3_8 is
begin
y0<=(not a) and (not b)and (not c) and en;
y1<=(not a) and (not b) and c and en;
y2<=(not a) and b and (not c) and en;

NITISH KUMAR 17/IEC/031

NITISH KUMAR 17/IEC/031

y3<=(not a) and b and c and en;

y4<=a and (not b) and (not c) and en;
y5<=a and (not b) and c and en;
y6<=a and b and (not c) and en;
y7<=a and b and c and en;
end data_flow;

output

RESULT:- The decoder 3-8 designed have been realized and simulated using VHDL codes.

NITISH KUMAR 17/IEC/031