CPE 6204 – Logic Circuits and Switching Theory

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Design of Combinational Circuits 2

Module 7: Design of Combinational Circuits 2

Course Learning Outcomes:

1. Explain the function of decoders, encoders, and multiplexers
2. Design and build decoders, encoders, and multiplexers
3. Use different design schemes to build standard components

Decoders
Discrete quantities of information are represented in digital computers with binary codes. A
binary code of 𝑛 bits can represent up to 2𝑛 distinct elements of the coded information.
A decoder is a combinational circuit that converts binary information from 𝑛 input lines to a
maximum of 2𝑛 unique output lines. If the 𝑛-bit coded information has unused combinations,
the decoder may have fewer than 2𝑛 outputs.
The decoders we will consider here are called 𝑛-to-𝑚-line decoders, where 𝑚 ≤ 2𝑛 . Their
purpose is to generate the 2𝑛 (or fewer) minterms of 𝑛 input variables. A decoder has 𝑛
inputs and 𝑚 outputs, also referred to as an 𝑛 × 𝑚 decoder. The name decoder is used in
conjunction with other code converters, such as BCD-to-seven-segment decoder.
Let us take a look at an example, a 3-to-8-line decoder circuit (Figure 1). The three inputs are
decoded into eight outputs, each representing one of the minterms of the three input
variables.
An application of this decoder is binary-to-octal conversion. The input variables represent a
binary number, and the outputs represent the eight digits of a number in the octal number
system. However, a three-to-eight decoder can be used for decoding any three-bit code to
provide eight outputs, one for each element of the code.
The operation of the decoder may be clarified by the truth table:
Table 1. Truth table of a 3-to-8 Line Decoder
Inputs Outputs
𝑥 𝑦 𝑧 𝐷0 𝐷1 𝐷2 𝐷3 𝐷4 𝐷5 𝐷6 𝐷7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

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 Figure 1. 3-to-8 Line Decoder

Some decoders are constructed with NAND gates. Since a NAND gate produces the AND
operation with an inverted output, it becomes more economical to generate the decoder
minterms in their complemented form. Furthermore, decoders include one or more enable
inputs to control the circuit operation. A two-to-four-line decoder with an enable input
constructed with NAND gates is shown in Figure 2. The circuit operates with complemented
outputs and a complement enable input. The decoder is enabled when 𝐸 is equal to 0. As
indicated by the truth table, only one output can be equal to 0 at any given time. The output
whose value is 0 represents the minterm selected by inputs A and B. the circuit is disabled
when 𝐸 is 1, regardless of the values of the other two inputs. When the circuit is disabled,
none of the outputs are equal to 0 and none of the minterms are selected.
In general, a decoder may operate with complemented or uncomplemented outputs. The
enable input may be activated with a 0 or with a 1 signal. Some decoders have two or more
enable inputs that must satisfy a given logic condition in order to enable the circuit
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Design of Combinational Circuits 2

Figure 2. 2-to-4-line Decoder

Table 2. Truth table of a 2-to-4 Decoder

Inputs Outputs
𝐸 𝑎 𝑏 𝐷0 𝐷1 𝐷2 𝐷3
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
A decoder with enable input can function as a demultiplexer – a circuit that receives
information from a single line and directs it to one of 2𝑛 possible output lines. The selection
of a specific output is controlled by the bit combination of 𝑛 selection lines. For example, the
2-to-4 decoder can function as a one-to-four-line demultiplexer when 𝐸 is taken as a data
input line and 𝐴 and 𝐵 are taken as the selection inputs. The single input variable 𝐸 has a
path to all four outputs, but the input information is directed to only one of the output lines,
as specified by the binary combination of the two selection lines 𝐴 and 𝐵.
Because decoder and demultiplexer operations are obtained from the same circuit, a decoder
with an enable input is referred to as a decoder-demultiplexer.

Encoders
An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder
has 2𝑛 (or fewer) input lines and 𝑛 output lines. The output lines, aggregated, generate the
binary code corresponding to the input value.
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An example of an encoder is the octal-to-binary encoder whose truth table is given in Table
3. It can be implemented with OR gates whose inputs are determined directly from the truth
table. The outputs are expressed by the following Boolean functions:
𝑧 = 𝐷1 + 𝐷3 + 𝐷5 + 𝐷7
𝑦 = 𝐷2 + 𝐷3 + 𝐷6 + 𝐷7
𝑥 = 𝐷4 + 𝐷5 + 𝐷6 + 𝐷7
Table 3. Truth table of an Octal-to-Binary Encoder
Inputs Outputs
𝐷0 𝐷1 𝐷2 𝐷3 𝐷4 𝐷5 𝐷6 𝐷7 𝑥 𝑦 𝑧
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
The encoder above has the limitation that only one input can be active at any given time. If
two inputs are active simultaneously, the output produces an undefined combination. To
solve this, encoder circuits must establish an input priority to ensure that only one input is
encoded.
Another ambiguity in the octal-to-binary encoder is that an output with all 000’s is generated
when all the inputs are 0; but this output is the same as when 𝐷0 = 1. This can be solved by
providing one more output to indicate whether at least one input is equal to 1.

Priority Encoders
A priority encoder is a circuit that includes the priority function. The operation of the priority
encoder is such that if two or more inputs are equal to 1 at the same time, the input having
the highest priority will take precedence. The truth table of a four-input priority encoder is
shown in Table 4 below. In addition to the two outputs 𝑥 and 𝑦, the circuit has a third output
designated by 𝑉; this is a valid bit indicator that is set to 1 when one or more inputs are equal
to 1. If all inputs are 0, there is no valid input and 𝑉 = 0.
According to the table, the higher the subscript number, the higher the priority of the input.
Table 4. Truth table of a four-input Priority Encoder
Inputs Outputs
𝑫𝟎 𝑫𝟏 𝑫𝟐 𝑫𝟑 𝒙 𝒚 𝑽
0 0 0 0 X X 0
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X X 1 0 1 0 1
X X X 1 1 1 1
Using maps to simplify the outputs, we arrive at the following Boolean functions:
𝑥 = 𝐷2 + 𝐷3
𝑦 = 𝐷3 + 𝐷1 𝐷2 ′
𝑉 = 𝐷0 + 𝐷1 + 𝐷2 + 𝐷3
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The logic diagram is illustrated below:

Figure 3. Four-input Priority Encoder

Multiplexers
Multiplexers are among the most commonly used combinational circuits. They choose an
output from among several possible inputs based on the value of a select signal. A multiplexer
is familiarly called mux.
Figure 4 shows a schematic diagram for a 2:1 multiplexer, and Table 5 shows its truth table.

Figure 4. Symbol of a 2:1 multiplexer

Table 5. Truth table of a 2:1 multiplexer

The multiplexer has two data inputs, 𝐷0 and 𝐷1 , a select input 𝑆, and one output 𝑌. The
multiplexer chooses between the two data inputs based on the select: if 𝑆 = 0, 𝑌 = 𝐷0 , and if
𝑆 = 1, 𝑌 = 𝐷1 . 𝑆 is also called a control signal because it controls what the multiplexer does.
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A 2:1 multiplexer can be built from the SOP logic 𝑌 = 𝐷0 𝑆 ′ + 𝐷1 𝑆. The Boolean equation for
the multiplexer may be derived with a K-map or can be read off by inspection.

Figure 5. Logic diagram of a 2:1 mux

Alternatively, multiplexers can be built from tristate buffers.

Figure 6. 2:1 mux implemented with tristate buffers

The tristate enables are arranged such that, at all times, exactly one tristate buffer is active.
When 𝑆 = 0, tristate T0 is enabled, allowing 𝐷0 to flow to Y. When 𝑆 = 1, tristate T1 is
enabled, allowing 𝐷1 to flow to Y.

A tristate buffer is a buffer with an Enable input that controls whether the primary input is
allowed to pass to the output or not. If the Enable signal is true, the tristate buffer behaves
like a normal buffer. If the Enable input signal is false, the tristate buffer passes a high
impedance (or hi-Z) signal, which effectively disconnects its output from the circuit (Bowler
Hat, LLC., n.d.)

Wider Multiplexers
A 4:1 multiplexer has four data inputs and one output. Two select signals are needed to
choose among the four data inputs. The 4:1 multiplexer can be built using SOP logic, tristates,
or multiple 2:1 multiplexers.

Figure 7. Symbol for a 4:1 mux

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Design of Combinational Circuits 2

Figure 9. 4:1 mux

implemented with tristate
buffers
Figure 8. 4:1 mux implemented with logic gates1

Figure 10. 4:1 mux implemented with 2:1 multiplexers

The product terms enabling the tristates can be formed using AND gates and inverters. They
can also be formed using a decoder.
Wider multiplexers, such as 8:1 and 16:1 can be built by expanding the methods shown in
the figures above. In general, an N:1 multiplexer needs log 2 𝑁 select lines. The best
implementation choice depends on the target technology.

1Some illustrations of logic gates do not have black-shaded “bubbles”. Most references use the bubbles only to
denote inversion, and these bubbles are unshaded (open hole). In this module, we have used gates with and
without shaded bubbles. Just note that only those with unshaded bubbles indicate inversion.
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 Multiplexer Logic
Multiplexers can be used as lookup tables to perform logic functions. Figure 11 shows a 4:1
mux used to implement a two-input AND gate. The inputs 𝐴 and 𝐵, serve as select lines. The
mux data inputs are connected to 0 or 1 according to the corresponding row of the truth
table. In general, a 2𝑛 -input multiplexer can be programmed to perform any 𝑁-input logic
function by applying 0’s and 1’s to the appropriate data inputs. By changing the data inputs,
the mux can be reprogrammed to perform a different function.

Figure 11. 4:1 mux implementation of 2-input AND function

Challenge! Try the following

1. Implement a two-input AND function with 2:1 multiplexers
2. Implement a two-input XOR function with 2:1 multiplexers
3. Implement the function 𝑌 = 𝐴𝐵′ + 𝐵′𝐶 ′ + 𝐴′𝐵𝐶 with an 8:1 multiplexer.

References and Supplementary Materials

Books and Journals
1. Mano, M. M., Ciletti, M.D. (2018). Digital Design: With an Introduction to the Verilog HDL,
VHDL, and SystemVerilog (6th ed.). New Jersey: Pearson.
2. Harris, D.M, Harris, S.L. (2016). Digital Design and Computer Architecture: ARM Edition.
Massachusetts: Elsevier Inc.
3. Roth, C.H. Jr., Kinney, L.L. (2014). Fundamentals of Logic Design (7th ed.). Connecticut:
Cengage Learning
Online Supplementary Reading Materials
1. What is an Encoder? https://www.allaboutcircuits.com/textbook/digital/chpt-
9/encoder/, Date Accessed: 19 October 2019
2. Decoder, https://www.allaboutcircuits.com/textbook/digital/chpt-9/decoder/, Date
Accessed: 19 October 2019

Online Instructional Videos

1. Multiplexers, https://ocw.mit.edu/courses/electrical-engineering-and-computer-
science/6-004-computation-structures-spring-2017/c4/c4s2/c4s2v6/, Date Accessed:
19 October 2019