EXPT.

NO: 06
SEC: A1

NAME OF THE EXPT: ARITHMATIC CIRCUIT DESIGN

ROLL NO: 0106031

OBJECTIVE:

The objective of this experiment is to design arithmetic circuits using logic gates and implement of
those circuits.

PROBLEMS:

1. Using IC-74154 design a 2-bit comparator to compare 2-bit numbers P and Q. The circuit
should provide 3 output lines to indicate P>Q, P=Q and P<Q
2. Design a 1-bit full sub tractor circuit using basic logic gates
3. Design a 4-bit CLA (Carry Look Ahead) adder circuit.

REQUIRED INSTRUMENTS:

No Name Model Quantity

1. Trainer Board 1 piece
2. IC – Extractor 1 piece
3. IC (4 to 16 Decoder) 74LS154 1 piece
4. IC ( Hex-Inverter) 74LS04 1 piece
5. IC (Quad 2 input AND) 74LS08 1 piece
6. IC (Quad 2 input OR) 74LS32 1 piece
7. IC (8 input NAND Gate) 74LS30 2 piece
8. IC (Dual 4 input NAND Gate) 74LS20 1 piece
9. IC (Quad 2 input XOR Gate) 74LS86 1 piece
10. IC (Look Ahead Carry Generator) 74LS182 1 piece
11. Wires A lot
12. Hand Book 1 piece
PROBLEM -01: Using IC-74154 design a 2-bit comparator to compare 2-bit numbers P and Q. The
circuit should provide 3 output lines to indicate P>Q, P=Q and P<Q

TRUTH TABLE:

A B f1 f2 f3
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

FUNCTION SIMPLIFICATION:
From the truth table we can see that,
F1 = m4  m8  m9  m12  m13  m14  m4  m8  m9  m12  m13  m14  M 4 M 8 M 9 M 12 M 13 M 14
F2 = m0  m5  m10  m15  m0  m5  m10  m15  M 0 M 5 M 10 M 15
F3 = m1  m2  m3  m6  m7  m11  m1  m2  m3  m6  m7  m11  M 1 M 2 M 3 M 6 M 7 M 11

CIRCUIT DIAGRAM AND PIN SPECIFICATIONS:

PROBLEM -02: Design a 1-bit full sub tractor circuit using basic logic gates

TRUTH TABLE:

X Y Z X-Y-Z
C S
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

FUNCTION MINIMIZATION:
From the truth table we can see that,
S = X’Y’Z + X’YZ’+XY’Z’+XYZ
=>S = Z(X’Y’+XY) +Z’(X’Y+XY’)
=>S=Z(XY)+Z’(XY)
=>S=Z(XY)’+Z’(XY)
=>S=XYZ
So S = XYZ

And
C=X’Y’Z+ X’YZ’+ X’YZ+ XYZ
=>C=Z(X’Y’+XY)+X’Y(Z+Z’)
=>C=Z(XY)+X’Y

So C= Z(XY)+X’Y

CIRCUIT DIAGRAM AND PIN SPECIFICATION:

PROBLEM -03: Design a 4-bit CLA (Carry Look Ahead) adder circuit.

Let, AA3A2A1A0 And BB3B2B1B0 are two 4-bit binary number.

TRUTH TABLE:
Ai Bi Ci Si
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

FUNCTION SIMPLIFICATION:
Pi  Carry Propagator
Gi  Carry Generator

And By definition,
Pi =Ai  Bi
G i = A i Bi
Si = Ai  Bi  Ci = Pi  Ci
Ci+1 = AiBi + (Ai  Bi) Ci = Gi + PiCi
Then,
1. P0 =A0B0 ; P1 =A1B1 ; P2 =A2B2 ; P3 =A3B3
2. G0=A0B0 ; G1=A1B1 ; G2=A2B2 ; G3=A3B3 ;
3. S0=P0C0 ; S1=P1C1 ; S2=P2C2 ; S3=P3C3 ;

C1 = G0 + P0C0
C2 = G1 + P1C1=G1+P1(G0 +P0C0)=G1+P1G0+P1P0C0
C3 = G2+P2C2=G2+ P2G1+P2P1G0+P2P1P0C0
C4 = G3+P3C3=G3+ P3G2+P3P2G1+P3P2P1G0+P3 P2 P1 P0 C0
And
If we consider, G=G3+P3G2+P3P2G1+P3P2P1G0 & P= P3 P2 P1 P0
C4 = G +C0P

CIRCUIT DIAGRAM AND PIN SPECIFICATIONS: