Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Name: Pavahaariny A/P Kathegesen

SID: EP01080940
Section: 05
Date: 27th April 2022

Title: Flip-Flops and Their Applications (Laboratory 8)

Objectives:
1. To construct and investigate the behavior of clocked D and JK flip-flops.
2. To design and analyze the operation of mod-10 counter and shift registers.

Pre-Lab:
Q1) Configure the block diagram in Figure 8.9 given in the Laboratory Manual to produce a
mod-10 counter, which counts from 0 to 9, and then repeats.

Figure 8.9: 7493 Block Diagram (Given in Laboratory Manual)

Figure 1: Configured block diagram which produce a mod-10 counter done by Pavahaariny
(EP01080940).

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Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Q2) Figure 8.10 shows a display circuit, which consists of 7448 seven-segment decoders,
several small-ohms resistors, and a 7-segment (common-cathode) display which was given 9
given in the Laboratory Manual. QD, QC, QB and QA are the inputs to this circuit. [This circuit
is already built inside the IDL800 experimenter, where QD QC QB QA are labelled as A B C
D.]

Figure 8.10: Display circuit (Given in Laboratory Manual)

a) Construct the truth table of this circuit. The truth table should consist of four inputs (QD,
QC, QB and QA) and seven outputs (g, f, e, d, c, b, a). [Note: For digit 6 display, the top
segment is OFF. For digit 9 display, the bottom segment is OFF.]
INPUTS OUTPUTS
𝑸𝑨 𝑸𝑩 𝑸𝑪 𝑸𝑫 a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 0 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 0 0 1 1

Table 1: Truth Table of display circuit in Figure 8.10 done by Pavahaariny (EP01080940).

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Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Figure 2: Digit display of circuit from number 0 till 9 based on the truth table’s output by
Pavahaariny (EP01080940).

b) What is the function of seven-segment decoder and resistors in this circuit?

i). Seven-Segment Decoder

Binary Coded Decimal (BCD) to 7-segment display decoder is a particular decoder that
converts binary coded decimals into a form that may be readily shown on a 7-segment
display. It is a digital gadget that displays decimal numbers, alphabets, and characters. The
7-Segment display is made up of 7 LED segments organized in the shape of number 8 shown
in the Figure 1 above.

ii). Resistors
To resist the current flow so that the LED’s will not burn due to over current.

Results for Task 1: D Flip-Flop

Figure 3: Block Diagram and Truth Table of D flip-flop

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Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Results for Task 2: 4-bit Shift Register

Figure 4: Logic circuit of the 4-bit shift register done by Pavahaariny (EP01080940).

Vcc LED 7 , 6 , 5 , 4

GND

PULSE SWITCH

CLR PR D
HIGH(1) (INPUT)

Figure 5: Constructed 4 bit Shift Register by Pavahaariny(EP01080940) with a 4-bit number

01112 .

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Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Two 74LS74 chips were used to build and test a 4-bit shift register. The push button on the
experimenter was used to produce the clocking signal in Figure 5. Later on, the shift register
was demonstrated to lab instructor. The given 4-bit number given by the lab instructor was
01112 to store the number in the register. The Clear (CLR) and Preset (PR) was set to HIGH
(1). Meanwhile the pulse switch or push button was pressed after the input value to be stored.
The LED’s would light up (1) or don’t light up (0) which shows the stored value.

Results for Task 3: JK Flip-Flop

Figure 6: Block Diagram and Truth Table of JK flip-flop

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Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Results for Task 4: Mod-10 counter

INPUTS OUTPUTS
𝑸𝑨 𝑸𝑩 𝑸𝑪 𝑸𝑫 a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 0 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
1 0 0 1 1 1 1 0 0 1 1

Table 2: Truth Table for the input values and output digital display done by Pavahaariny
(EP01080940).

Figure 7: Shows how each count is displayed on the seven-segment display based on truth
table output done by Pavahaariny (EP01080940).

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Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Figure 8: Shows how’s the circuit to be constructed done by Pavahaariny (EP01080940).

Vcc

DIGITAL
DISPLAY
GND

AND Gate (7408)

PULSE SWITCH

Figure 9: Mod-10 counter display count number “0” is displayed on the seven-segment
display done by Pavahaariny (EP01080940).

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Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Figure 10: Mod-10 counter count display number “1” is displayed on the seven-segment
display done by Pavahaariny (EP01080940).

Figure 11: Mod-10 counter count number display “2” is displayed on the seven-segment
display done by Pavahaariny (EP01080940).

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Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Figure 12: Mod-10 counter count number display “3” is displayed on the seven-segment
display done by Pavahaariny (EP01080940).

Figure 13: Mod-10 counter count number display “4” is displayed on the seven-segment
display done by Pavahaariny (EP01080940).

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Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Figure 14: Mod-10 counter count number display “5” is displayed on the seven-segment
display done by Pavahaariny (EP01080940).

Figure 15: Mod-10 counter count number display “6” is displayed on the seven-segment
display done by Pavahaariny (EP01080940).

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Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Figure 16: Mod-10 counter count number display “7” is displayed on the seven-segment
display done by Pavahaariny (EP01080940).

Figure 17: Mod-10 counter count number display “8” is displayed on the seven-segment
display done by Pavahaariny (EP01080940).

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Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Figure 18: Mod-10 counter count number display “9” is displayed on the seven-segment
display done by Pavahaariny (EP01080940).

Implementation of Mod-10 counter, is when counters 0-9 counts from using 7493 chip and AND
logic gate (7408). The mod-10 counter designed from pre-lab Question 1 was. The toggle switch
was used on the experimenter to produce the clocking signal. The outputs of 7493 counter were
connected to the inputs (DCBA) of seven-segment display circuits. Later on, the mod-10 counter
demonstrated to the lab instructor. Finally, by drawing each count displayed on the seven-segment
display were able and drawn.

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Logbook for Digital Logic Design Laboratory (EEEB161 / EEEB1041)

Post-Lab:
Q1) Can you modify the above Mod-10 counter to count down rather than up. Justify.

A positive edge triggered counter will count down from 11112 to 00002 by collecting both the
output lines and the CK pulse for the next flip-flop in sequence from the Q output. Although
both up and down counters can be built using the asynchronous method of clock propagation,
it is not widely used as counters because the clock ripple effect causes it to become unreliable
at high clock speeds or when a large number of flip-flops are connected together to give larger
counts.

Conclusion:
Finally, the Flip Flop D and JK flip were able to be constructed and investigate its
behaviour of its clocked. Meanwhile, the circuit was able to be constructed based on the input and
output value of the truth table. Last but not least, the operation of mod-10 counter and shift registers
were able to be design and analyze. While constructing the circuit for mod-10 counter and shift
registers few troubleshooting process was carried out, through this process mistake were able to
be identified and solved immediately.

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