Solution of Digital Circuit and Logic Design 1 Page 1/10

Homework#06 2005/2

Solution of Homework#06

(1) Draw block diagram to show how to use 3-to-8 lines decoders to produce the
following:
(All decoders have one active-low ENABLE input, active-high binary code inputs,
and active-low outputs. You can use additional components if required)
(a) A 4-to-16 line decoder

(b) A 6-to-64 line decoder

Panupong Sornkhom Department of Electrical and Faculty of Engineering,

Computer Engineering Naresuan University
Solution of Digital Circuit and Logic Design 1 Page 2/10
Homework#06 2005/2

(2) Show how to build each of the following single- or multiple-output logic functions
using one or more 74x138 binary decoders and NAND gates.
(Hint: Each realization should be equivalent to a sum of minterms.)
(a) F = ΣX,Y,Z(2,4,7)

(b) F= ∏A,B,C(3,4,5,6,7)

(c) F = ΣA,B,C,D(2,4,6,14)

Panupong Sornkhom Department of Electrical and Faculty of Engineering,

Computer Engineering Naresuan University
Solution of Digital Circuit and Logic Design 1 Page 3/10
Homework#06 2005/2

(d) F = ΣW,X,Y(1,3,5,6) and G = ΣW,X,Y(2,3,4,7)

(e) F = ΣA,B,C(0,4,6) and G = ΣC,D,E(1,2)

(3) Using MSI 74x49 BCD to seven-segment decoder and additional hardware to
build a new seven-segment decoder such that the digits 6 and 9 have tails as shown
below.

Seven-segment display

Panupong Sornkhom Department of Electrical and Faculty of Engineering,

Computer Engineering Naresuan University
Solution of Digital Circuit and Logic Design 1 Page 4/10
Homework#06 2005/2

The truth table of modified BCD-to-seven-segment decoder is shown below

Function Inputs Outputs

or D C B A BI_L na nb Nc nd ne nf ng
Decimal
0 0 0 0 0 1 1 1 1 1 1 1 0
1 0 0 0 1 1 0 1 1 0 0 0 0
2 0 0 1 0 1 1 1 0 1 1 0 1
3 0 0 1 1 1 1 1 1 1 0 0 1
4 0 1 0 0 1 0 1 1 0 0 1 1
5 0 1 0 1 1 1 0 1 1 0 1 1
6 0 1 1 0 1 1 0 1 1 1 1 1
7 0 1 1 1 1 1 1 1 0 0 0 0
8 1 0 0 0 1 1 1 1 1 1 1 1
9 1 0 0 1 1 1 1 1 1 0 1 1
10 1 0 1 0 1 0 0 0 1 1 0 1
11 1 0 1 1 1 0 0 1 1 0 0 1
12 1 1 0 0 1 0 1 0 0 0 1 1
13 1 1 0 1 1 1 0 0 1 0 1 1
14 1 1 1 0 1 0 0 0 1 1 1 1
15 1 1 1 1 1 0 0 0 0 0 0 0
BI X X X X 0 0 0 0 0 0 0 0

(4) Suppose you would like to use seven-segment display to show characters A, B, C,
D, E and F. So you have to design the code converter circuit to convert binary code
inputs to seven-segment code outputs. If the circuit has an active-high “lamp test”
input which force all LEDs on, and the active-low “blank input” input which force all
LEDs off except “lamp test” is asserted. Show the truth table, simplified AND-OR
logic diagram, and seven-segment display of each character.

A= B= C= D= E= F=

Panupong Sornkhom Department of Electrical and Faculty of Engineering,

Computer Engineering Naresuan University
Solution of Digital Circuit and Logic Design 1 Page 5/10
Homework#06 2005/2

The truth table is shown below

Function Inputs Outputs

or C B A LT BI_L na nb Nc nd ne nf ng
Character
A 0 0 0 0 1 1 1 1 0 1 1 1
B 0 0 1 0 1 1 1 1 1 1 1 1
C 0 1 0 0 1 1 0 0 1 1 1 1
D 0 1 1 0 1 1 1 1 1 1 1 0
E 1 0 0 0 1 1 0 0 1 1 1 1
F 1 0 1 0 1 1 0 0 0 1 1 1
- 1 1 0 0 1 d d D D d d d
- 1 1 1 0 1 d d D D d d d
BI X X X 0 0 0 0 0 0 0 0 0
LT X X X 1 X 1 1 1 1 1 1 1

Each output is in form of LT+BI·m where m is a logic function of

minterm.

Panupong Sornkhom Department of Electrical and Faculty of Engineering,

Computer Engineering Naresuan University
Solution of Digital Circuit and Logic Design 1 Page 6/10
Homework#06 2005/2

(5) Draw the logic diagram for a 8-to-3 encoder using just three 4-input NAND gates.
What are the active levels of the inputs and outputs in your design?

Inputs are active low and outputs are active high.

(6) A customized priority encoder is defined in the table below; show the simplified
NAND-NAND circuit corresponding to such priority encoder.

Inputs Outputs
EN RI2 RI1 RI0 Y1 Y0 RO
0 X X X 0 0 0
1 1 X X 1 0 1
1 0 1 X 0 1 1
1 0 0 1 1 1 1
1 0 0 0 0 0 0

Panupong Sornkhom Department of Electrical and Faculty of Engineering,

Computer Engineering Naresuan University
Solution of Digital Circuit and Logic Design 1 Page 7/10
Homework#06 2005/2

(7) Write the minimal sum expression of 8-to-1 multiplexer with one enable input EN,
eight data inputs D7-D0, three selecting inputs S2-S0, and one output Y. (all inputs
and outputs are active-high.)

The truth table of 8-to-1 multiplexer is shown below

Inputs Outputs
EN S2 S1 S0 Y
0 X X X 0
1 0 0 0 D0
1 0 0 1 D1
1 0 1 0 D2
1 0 1 1 D3
1 1 0 0 D4
1 1 0 1 D5
1 1 1 0 D6
1 1 1 1 D7
From the truth table
Y = EN·S2′·S1′·S0′·D0 + EN·S2′·S1′·S0·D1 + EN·S2′·S1·S0′·D2 + EN·S2′·S1·S0·D3
+ EN·S2·S1′·S0′·D4 + EN·S2·S1′·S0·D5 + EN·S2·S1·S0′·D6 + EN·S2·S1·S0·D7

Panupong Sornkhom Department of Electrical and Faculty of Engineering,

Computer Engineering Naresuan University
Solution of Digital Circuit and Logic Design 1 Page 8/10
Homework#06 2005/2

(8) Use 4-to-1 multiplexer to implement the following:

(All multiplexer have one active-low ENABLE input, active-high data inputs, active-
high selector inputs, and active-high data output. You can use additional components
if required)
(a) 16-to-1 multiplexer

(b) 32-to-1 multiplexer

Panupong Sornkhom Department of Electrical and Faculty of Engineering,

Computer Engineering Naresuan University
Solution of Digital Circuit and Logic Design 1 Page 9/10
Homework#06 2005/2

(9) Show how to build each of the following logic functions using 4-to-1 multiplexer
and additional gates.
(a) F = ΣX,Y,Z(2,4,7)

YZ X Minterm F D
00 0 0 0 X
1 4 1
01 0 1 0 0
1 5 0
10 0 2 1 X′
1 6 0
11 0 3 0 X
1 7 1

(b) F= ∏A,B,C(3,4,5,6,7)

BC A Minterm F D
00 0 0 0 A
1 4 1
01 0 1 0 A
1 5 1
10 0 2 0 A
1 6 1
11 0 3 1 1
1 7 1

(c) F = ΣA,B,C,D(2,4,6,14)

CD AB Minterm F D
00 00 0 0 A′·B
01 4 1
10 8 0
11 12 0
01 00 1 0 0
01 5 0
10 9 0
11 13 0
10 00 2 1 A′+B
01 6 1
10 10 0
11 14 1
11 00 3 0 0
01 7 0
10 11 0
11 15 0

Panupong Sornkhom Department of Electrical and Faculty of Engineering,

Computer Engineering Naresuan University
Solution of Digital Circuit and Logic Design 1 Page 10/10
Homework#06 2005/2

(d) Odd parity generator for 4 information bits

F = ΣA,B,C,D(0,3,5,6,9,10,12,15)

CD AB Minterm F D
00 00 0 1 A′·B′ +
01 4 0 A·B
10 8 0 =(A⊕B)′
11 12 1
01 00 1 0 A′·B +
01 5 1 A·B′
10 9 1 =A⊕B
11 13 0
10 00 2 0 A′·B +
01 6 1 A·B′
10 10 1 =A⊕B
11 14 0
11 00 3 1 A′·B′ +
01 7 0 A·B
10 11 0 =(A⊕B)′
11 15 1

(10) Implement 1-to-8 demultiplexer which all pins are active-high; using only one
74x139 IC and additional gates, show the logic diagram in bubble-to-bubble logic
design form.

Data 1/2 74x139 Y0

1 5
a1
G Y0
b1
Y1
A 2
a2
A Y1
b2
6

Y2
3
a3 B Y2
b3
7

B Y3
Y3
b4
8

Y4
C
Y5
1/2 74x139
1
a1
G Y0
b1
5 Y6
2
a2
A Y1
b2
6
Y7
3
a3 B Y2
b3
7

Y3
b4
8

Panupong Sornkhom Department of Electrical and Faculty of Engineering,

Computer Engineering Naresuan University