DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

 DIGITAL ELECTRONICS

Combinational Logic Modules

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
DIGITAL ELECTRONICS
Definition of Combinational Logic

❖ Definition

Digital Circuits

Combinational Sequential
DIGITAL ELECTRONICS
Different Combinational Logic Modules

❖ Adders

❖ Subtractors

❖ Comparators

❖ Decoders

❖ Encoders

❖ Multiplexers & Demultiplexers

❖ PLDs etc.
 DIGITAL ELECTRONICS
Carry Look-Ahead Adder(CLAA)
❖ Motivation behind CLAA(Look Ahead Carry Generators)
❖ Serial v/s Parallel adders

1101 A3 A2 A1 A0 13
1011 B3 B2 B1 B0 11
1 1 0 0 0 Cout S3 S2 S1 S0 24
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Design of CLAA

❖ Limitations of Parallel adders?

❖ How CLAA overcome this?

❖ What CLAA consisting of?

 DIGITAL ELECTRONICS
Design of CLAA

❖ From the basics of Full adder , the SUM & CARRY expressions
after simplification(K-Maps)are:

➢ Sum=AꚚB ꚚCin

➢ Carry=AB+BCin+ACin
=AB+Cin(A+B)

Here AB is carry generating function(g) & (A+B) is carry

propagating function(p).
 DIGITAL ELECTRONICS
Design of CLAA for ith –order Parallel adder

Carry Ci+1=gi+piCi

For LSB FA, i=0

C1=g0+p0C0
Where C0 is initial carry for LSB (first)FA
C1 is carry for second FA

C0
p0

C1
g0

Implementation of C1
DIGITAL ELECTRONICS
Design of CLAA for ith –order Parallel adder

For next FA, i=1

C2=g1+p1C1,where C1=g0+p0C0
C2=g1+p1(g0+p0C0)
C2 is carry for third FA

C0
p0
p1

g1 C2

g0
p1
 DIGITAL ELECTRONICS
Design of CLAA for ith –order Parallel adder

For next FA, i=2

C3=g2+p2C2,where C2=g1+p1(g0+p0C0)

C3=g2+p2[(g1+p1(g0+p0C0)

C3 is carry for fourth FA

Similarly, we can implement C3which uses 3 AND gates

and 1 OR gate.
 DIGITAL ELECTRONICS
Overall circuit diagram of 4-Bit CLAA

C1=g0+p0C0
C2=g1+p1(g0+p0C0)
C3=g2+p2[(g1+p1(g0+p0C0)

C3

p2
g2

C2
p1
g1
p0
g0 C1
C0
 DIGITAL ELECTRONICS
Carry Look Ahead Adders

Advantages and Disadvantages of Carry Look-Ahead Adder :

❖ Advantages
• The propagation delay is reduced.
• It provides the fastest addition logic.

❖ Disadvantages
• The Carry Look-ahead adder circuit gets complicated as the
number of variables increase.
• The circuit is costlier as it involves more number of hardware.
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@[Link]
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

 DIGITAL ELECTRONICS

Combinational Logic Modules

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS
DECIMAL ADDERS CONCEPTS

❖BCD ADDERS

Coded version of Decimal numbers

❖BCD numbers vary from 0 to 9(i e 0000 to 1001)

❖Expected Max. Sum of adding two BCD numbers is

9+9+1=19

❖ To add two Decimal numbers & to get valid BCD sum,need to

design a Decimal Adder/BCD Adder.
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Design of BCD/Decimal Adder

❖ For example, adding two decimal numbers say 3 & 4:

❖ We need a 4-bit parallel adder since

3---0011
4---0100
7---0111---Valid BCD sum

❖ For example, adding two decimal numbers say 7 & 9:

7---0111
9---1001
16—10000-Invalid BCD sum
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Design of BCD/Decimal Adder

❖ Representing 16 as valid BCD needs subtraction of 10 from it.

❖ 2’s complemented subtraction

❖ Adding 6(0110) to invalid BCD

❖ Based on this concept, need to design a logic with parallel

adder to convert Invalid BCD sum to valid BCD
 DIGITAL ELECTRONICS
Design of BCD/Decimal Adder

Problem statement to design Correction Logic for Decimal Adder:

❑ Design a logic which accepts four inputs(sum o/p of parallel

adder i.e S3 S2 S1 S0) & gives out one o/p,whose o/p goes high
when sum exceeds 9 or invalid BCD.

❑ Steps in Designing
1. Construct Truth Table
2. Write SOP Expression
3. Simplify using K-map
4. Implement logic with Adder

NOTE:End carry Cout is default variable added with correction

logic
DIGITAL ELECTRONICS
Design of BCD/Decimal Adder
Decimal Binary Sum BCD Sum O/P
Cout S3 S2 S1 S0 Cout S3 S2 S1 S0 f
0 0 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 1 0 0 0 0 1 0
2 0 0 0 1 0 0 0 0 1 0 0

3 0 0 0 1 1 0 0 0 1 1 0
4 0 0 1 0 0 0 0 1 0 0 0
5 0 0 1 0 1 0 0 1 0 1 0
6 0 0 1 1 0 0 0 1 1 0 0
7 0 0 1 1 1 0 0 1 1 1 0
8 0 1 0 0 0 0 1 0 0 0 0
9 0 1 0 0 1 0 1 0 0 1 0
10 0 1 0 1 0 1 0 0 0 0 1
11 0 1 0 1 1 1 0 0 0 1 1
12 0 1 1 0 0 1 0 0 1 0 1
13 0 1 1 0 1 1 0 0 1 1 1
14 0 1 1 1 0 1 0 1 0 0 1
15 0 1 1 1 1 1 0 1 0 1 1
16 1 0 0 0 0 1 0 1 1 0 1
17 1 0 0 0 1 1 0 1 1 1 1
18 1 0 0 1 0 1 1 0 0 0 1
19 1 0 0 1 1 1 1 0 0 1 1
 DIGITAL ELECTRONICS
Design of BCD/Decimal Adder

The SOP Expression is f(S3,S2,S1,S0)=∑m(10,11,12,13,14,15)

S3S2 S1S0
S1’S0’ S1’S0 S1S0 S1S0’

S3’S2’ 0 0 0 0

S3’S2 0 0 0 0
S3S2
S3S2 1 1 1 1
S3S1

S3S2’ 0 0 1 1

The Correction Logic is f=S3S2+S3S1+Cout

DIGITAL ELECTRONICS
Design of BCD/Decimal Adder
 DIGITAL ELECTRONICS
Design of BCD/Decimal Adder

Analysis to know the working of CLAA with an example:

Let us take two BCD numbers A & B

A-------8--------1 0 0 0
B-------9--------1 0 0 1
17 1 0 0 0 1---Invalid BCD
+0 0 1 1 0
000 1 0 1 1 1

1 7

In this case the logic o/p will be 1

 DIGITAL ELECTRONICS
Design of BCD/Decimal Adder

Let us take two BCD numbers A & B for another example:

A-----4--------0100
B-----3--------0011
7 0111---Valid BCD
+0000
0111

So that in this case the logic o/p is 0

 DIGITAL ELECTRONICS
BCD/Decimal Adder
❑ The BCD-Adder is used in the computers and the calculators
that perform arithmetic operation directly in the decimal
number system.

❑ The BCD-Adder accepts the binary-coded form of decimal

numbers.

❑ The Decimal-Adder requires a minimum of nine inputs and five

outputs.
 DIGITAL ELECTRONICS
BCD/Decimal Adder

BCD/Decimal Adder Summary:

❖ BCD adder A 4-bit binary adder that is capable of adding two
4-bit words having a BCD (binary-coded decimal) format.

❖ The result of the addition is a BCD-format 4-bit output word,

representing the decimal sum of the addend and augend, and
a carry that is generated if this sum exceeds a decimal value of
9.

❖ Decimal addition is thus possible using these devices.

THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@[Link]
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Combinational Logic Modules

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS
Comparators

• A comparator is a combinational circuit which take ‘n’ number

of inputs and always gives 3 outputs
1. Greater than
2. Equal to
3. Less than
DIGITAL ELECTRONICS
Comparators
1-Bit Comparator
• It compares 2 binary numbers of each one bit.
• It has 2 inputs and 3 outputs. Truth table is as follows

A B A>B A=B A<B

0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0

Output Equations:
1.A>B➔AB’
2.A=B➔A’B’ + AB
3.A<B→A’B
DIGITAL ELECTRONICS
Comparators

[(A<B)+(A>B)]=(A’B+AB’)
Taking complement on both sides,
[(A<B)+(A>B)]’=(A’B +AB’)’
[(A<B)+(A>B)]’=(A’B)’.(AB’)’
{Using DeMorgan’s Theorem (A+B)’=A’B’}
[(A<B)+(A>B)]’=[(A’)’+B’].[A’+(B’)’]
{Using DeMorgan’s Theorem (AB)’=A’+B’}
[(A<B)+(A>B)]’=[A+B’].[A’+B]
[(A<B)+(A>B)]’=AB+A’B’
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Comparators

CIRCUIT DIAGRAM
 DIGITAL ELECTRONICS
Comparators
2-Bit Comparator
• It compare two binary numbers each of 2 bits. Truth table is as
follows:
 DIGITAL ELECTRONICS
Comparators

Output Equations from K-Maps:

1.(A<B):
(A<B)=A1’B1 + A0’B1B0 + A1’A0’B0
 DIGITAL ELECTRONICS
Comparators

2.(A=B):
(A=B)→A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’
→A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)
(A=B)→(A0B0 + A0’B0’) (A1B1 + A1’B1’)
 DIGITAL ELECTRONICS
Comparators

3.(A>B):
(A>B)=A1B1’ + A0B1’B0’ + A1A0B0’
DIGITAL ELECTRONICS
Comparators

CIRCUIT DIAGRAM:
 DIGITAL ELECTRONICS
Comparators
CASCADED COMPARATORS:

❖A comparator performing the comparison operation to more

than four bits by cascading two or more 4-bit comparators is
called cascading comparator.

❖When two comparators are to be cascaded, the outputs of the

lower-order comparator are connected to corresponding inputs
of the higher-order comparator.
 DIGITAL ELECTRONICS
Comparators
CIRCUIT DIAGRAM:8-Bit Comparator
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@[Link]
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Combinational Logic Modules

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS
DECODERS

• They are MINTERM GENERATORS and convert decimal to binary.

• In general there are N input lines and 2N output lines.
• It internally consists of AND gates and INVERTERS.
DIGITAL ELECTRONICS
DECODERS

2:4 line binary Decoder:

DIGITAL ELECTRONICS
DECODERS

Based on the internal and external architecture of a decoder ,

logic design can be done in the following ways-

Internally Externally Type of logic Implementation

AND OR SOP

AND NOR POS

NAND AND POS

NAND NAND SOP

 DIGITAL ELECTRONICS
DECODERS in Logic Design

Example1: Implement the following Boolean functions using a

suitable decoder and external logic if any.

1.f1(a, b, c)=Ʃm(0, 1, 3, 4)
2. f2(a, b, c)=Ʃm(2, 5, 6, 7)

NOTE: By default , if nothing is given, internally [Link] its SOP

expression, externally there should be OR gates. There are 3
inputs. We require a 3:8 line decoder.
DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS
LOGIC DIAGRAM
DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS

Example2: f1(a, b, c)=πM(1, 3, 5, 6, 7)

f2(a, b, c)=πM(1, 2, 3, 4)

By default its internally AND. As the given expression is POS,

externally there should be NOR gates. There are 3 inputs. We
require a 3:8 line decoder.
DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS

LOGIC DIAGRAM
 DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS

EXAMPLE 3:f1(a, b, c)=Ʃm(1, 3, 5, 6, 7)

f2(a, b, c)=Ʃm(0, 2, 3, 5, 6, 7)
Implement the above Boolean functions using a suitable decoder
by minimizing the number of inputs to gates to be summed.

❖There are 3 inputs. We require a 3:8 line decoder.

❖To minimize the number of inputs externally to the gates to be

summed.

❖Take canonical complementation of the given Boolean

functions.
 DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS

→f1(a, b, c)=πM(0, 2, 4)
→ f2(a, b, c)=πM(1, 4)
❖By default, its internally AND architecture.

❖To get the canonical complementation of the Boolean function,

take complementation of the external gates.

❖Externally there should be NOR gates since canonical

complemented Boolean function is in POS logic.
DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS

LOGIC DIAGRAM:
 DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS
EXAMPLE 4: f1(a, b, c)=Ʃm(1, 2, 3)
f2(a, b, c)=Ʃm(4, 5, 6)
Implement the above Boolean functions with a suitable Decoder
having complemented outputs.
❖There are 3 inputs. We require a 3:8 binary Decoder.

❖To get complementary outputs, the internal architecture has

to be NAND.

❖Externally , we should connect NAND gates as the given

expression is for SOP logic.
 DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS
Logic diagram:
 DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS

EXAMPLE 5:f1(a, b, c)=πM(1, 2, 3, 4)

f2(a, b, c)=πM(4, 5, 6, 7)
Implement the given Boolean functions using a suitable decoder
with active low outputs.
❖There are 3 inputs. We require a 3:8 line binary Decoder.

❖To get active low outputs, internally there will be NAND gates.

❖Externally we should connect AND gates as the given Boolean

expression is in POS logic.
 DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS
LOGIC DIAGRAM:
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@[Link]
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Combinational Logic Modules

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS
ENCODERS

❖ An Encoder is a combinational logic circuit that converts the

binary information from 2N input lines to N output lines.

❖ It helps in conversion of decimal to binary.

❖ Widely used is Octal-Binary (8:3) Encoder.

❖ It has 8 input line, 3 output lines.

 DIGITAL ELECTRONICS
ENCODERS

• Block diagram of 8:3 Octal-Binary Encoder and the

truth-table is as follows:
DIGITAL ELECTRONICS
ENCODERS
D7 D6 D5 D4 D3 D2 D1 D0 X Y Z

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1
DIGITAL ELECTRONICS
ENCODERS

❖The encoders internally has OR gates.

DIGITAL ELECTRONICS
ENCODERS

From the fig we observe that,

❖Only one input can be active at a given time for an

encoder .

❖If both D6 and D3 are active, then the actual output is

111 which is the output for D7.

❖To avoid this confusion, PRIORITY ENCODERS are used.

DIGITAL ELECTRONICS
ENCODERS

PRIORITY ENCODERS
❖When more than one input is active at a given time,
the input with highest priority takes precedence and
corresponding output is generated.

❖In case of normal encoders, when all the inputs are

zeros, the encoder output “000”which is also the
output for state D0.

❖To avoid this confusion, a validity bit is added to the

output which takes “0”if all the inputs are zeros and
“1”otherwise.
DIGITAL ELECTRONICS
ENCODERS

• Highest priority 4:2 Encoder

• Truth table is as follows:
• ‘X’ indicates don’t care
D3 D2 D1 D0 X Y Validity
Indicator
(V)

0 0 0 0 X X 0

0 0 0 1 0 0 1

0 0 1 X 0 1 1

0 1 X X 1 0 1

1 X X X 1 1 1
 DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS

Output Equations using K-Maps

1. Validity Indicator(V)
• ➔ V=D0+D1+D2+D3
DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS

• →For output X=D2+D3

DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS

→For output Y=D1D2’+D3

 DIGITAL ELECTRONICS
LOGIC DESIGN USING DECODERS

• CIRCUIT DIAGRAM
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@[Link]
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Combinational Logic Modules

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
DIGITAL ELECTRONICS
MULTIPLEXERS

❖It’s a combinational logic circuit having ‘2N’ input lines and a

single output depending on the ‘N’ select/control lines. Hence,
commonly known as ‘Data Selector’.
2:1 MUX:
 DIGITAL ELECTRONICS
MULTIPLEXERS
• From the fig, A and B are input. If select line is ‘0’, then A is
selected as output and if the select line is ‘1’, then B is the
output.
OUTPUT EQUATION FROM K-MAP:
S A’B’ A’B AB AB’
S’ 0 0 1 1
S 0 1 1 0

→Z=AS’+BS
CIRCUIT DIAGRAM:
 DIGITAL ELECTRONICS
MULTIPLEXERS

4:1 MUX:

• It has 4 inputs, 2 select lines and 1 output.

 DIGITAL ELECTRONICS
MULTIPLEXERS

TRUTH TABLE FOR 4:1 MUX:

S0 S1 I0 I1 I2 I3 Y

0 0 1 X X X I0

0 1 X 1 X X I1

1 0 X X 1 X I2

1 1 X X X 1 I3

OUTPUT EQUATION:
Y=S0’S1’I0+S0’S1I1+S0S1’I2+S0S1I3
 DIGITAL ELECTRONICS
MULTIPLEXERS

CIRCUIT DIAGRAM:
 DIGITAL ELECTRONICS
MULTIPLEXERS

4:1 MUX USING 2:1 MUX:

 DIGITAL ELECTRONICS
MULTIPLEXERS

8:1 MUX USING 4:1 MUX and 2:1 MUX

DIGITAL ELECTRONICS
MULTIPLEXERS

16:1 MUX USING 4:1 MUX:

THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@[Link]
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Combinational Logic Modules

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

1. Direct Implementation Technique

In this method,
❖The inputs are straight away taken on the select lines i.e
number of inputs in SOP/POS expression=Number of select
lines.

❖The required multiplexer is decided based on the number of

select lines.

❖Expected output is directly connected to the inputs of the

multiplexer.

❖Draw the Logic diagram representation.

 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS
EXAMPLE 1:Implement the following Boolean Function using
8:1MUX.
f(a, b, c)=Ʃ𝑚 1,2,5,6,7
DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

EXAMPLE 2:Implement the following Boolean Function using

4:1MUX.
f(a, b)=Ʃ𝑚 1,2
DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

2. Sub-Map Generation Technique

Steps to be followed
i. Construct K-Map for the given SOP expression
ii. Generate sub-maps on the main map in terms of the variables
present on the select lines(map variables)
iii. Note the variables absent on the select lines are residue variables.
Iv. Compare the function value present inside sub-map with values
of residue variables and connect MUX inputs with the compared
inputs of residue variables.
v. Draw Block Diagram Representation.
DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS
EXAMPLE 1:Implement the following Boolean Function using
4:1MUX.
f(a, b, c)=Ʃm (1, 2, 5, 6, 7).
There are 3 input variables. Consider a, b on select lines and c as
residue variable.
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

Logic Diagram:
DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

EXAMPLE 2:Implement the following Boolean Function using

8:1MUX.
f(a, b, c , d)=Ʃm(2, 4, 6, 8, 10, 12, 14)
Choose a, b, c on select lines and d as residue variable.
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS
Logic Diagram :
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@[Link]
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Combinational Logic Modules

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

EXAMPLE 3:Implement the following Boolean Function using

4:1MUX.
f(a, b, c , d)=Ʃm(4, 5, 7, 8, 12, 15)
Choose a, b on select lines of 4:1 MUX and c, d as residue
variables.
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

Logic Diagram:
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

EXAMPLE 4:Implement the following Boolean Function using

4:1MUX.
f(a, b, c , d)=Ʃm(0, 1, 3, 5, 7, 9, 11, 13, 15)
Choose c, d as select lines and a, b as residue variables.
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

Logic diagram :
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

EXAMPLE 4:Implement the following Boolean Function using

4:1MUX.
f(a, b, c , d)=Ʃm(0, 1, 3, 5, 7, 9, 11, 13, 15)
Choose a, d as select lines and b, c as residue variables.
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

Logic diagram:
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

Full Adder using 4 to 1 Multiplexer:

❖ In this logic, A,B,Cin are the inputs and S,Cout are the outputs.
Now implementation function for sum and carry out are as
follows.

➢ S(A,B,Cin)= ∑(1,2,4,7)

➢ Cout(A,B,Cin)= ∑(3,5,6,7)
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

Full Subtractor using 4 to 1 Multiplexer:

❖ In this logic, A,B,Bin are the inputs and Diff & Bout are the
outputs. Now implementation function for sum and carry out
are as follows.
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

APPLICATIONS OF MULTIPLEXER:

❖ Multiplexer circuits find numerous applications in digital

systems. Some of the fields where multiplexing finds immense
use are data selection, data routing, operation sequencing,
parallel-to-serial conversion, waveform generation and logic
function generation.

❖ Also a Multiplexer is used in various applications wherein

multiple data can be transmitted using a single line. They are:
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

1. Communication System – A Multiplexer is used in

communication systems, which has a transmission system and
also a communication network. A Multiplexer is used to
increase the efficiency of the communication system by
allowing the transmission of data, such as audio & video data
from different channels via cables and single lines.

2. Computer Memory – A Multiplexer is used in computer

memory to keep up a vast amount of memory in the
computers, and also to decrease the number of copper lines
necessary to connect the memory to other parts of the
computer.
 DIGITAL ELECTRONICS
Logic Design Using MULTIPLEXERS

3. Telephone Network – A multiplexer is used in telephone

networks to integrate the multiple audio signals on a single line
of transmission.

4. Transmission from the Computer System of a Satellite – A

Multiplexer is used to transmit the data signals from the
computer system of a satellite to the ground system by using a
GSM communication.
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@[Link]
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Combinational Logic Modules

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS
Programmable Logic Devices(PLDs)

❖In digital logic using Large Scale Architecture having 100-1000

BJTs.

❖Manual troubleshooting is difficult and hence devices are

programmed which can be either connected or disconnected to
circuit. They are called Programmable Logic Devices(PLDs).

❖PLDs consists of AND-OR technology in which either of the two

gates are mask programmable or field programmable.
 DIGITAL ELECTRONICS
Programmable Logic Devices(PLDs)

❖In mask programmable, changes can be made by manufacturer

and is not user friendly.

❖In field programmable, there will be programming connections

where changes can be by either making or breaking the circuit.

❖Fixed connections are represented by

❖Editable/changeable connections are represented by X.

 DIGITAL ELECTRONICS
Programmable Logic Devices(PLDs)

❖PLDs are classified into

1. PROM PLD(Programmable Read Only)
2. PAL (Programmable Array Logic)
3. PLA(Programming Logic Array)
Comparison between different types of PLDs
TYPE OF PLD PROM PAL PLA

AND FIXED PROGRAMMABLE PROGRAMMABLE

OR PROGRAMMABLE FIXED PROGRAMMABLE

 DIGITAL ELECTRONICS
Programmable Read Only Memory(PROM PLD)
❖To implement the given digital logic,Boolean Function should be
expressed in Canonical form.

❖For given ‘n ‘variables in the input, there are 2n AND gates and ‘n’
INVERTERS.

❖For ‘m’ number of Boolean expressions, there are ‘m’ OR gates.

❖In general PROM PLD structure is generally denoted by 2n * m

PROM PLD.
DIGITAL ELECTRONICS
Programmable Read Only Memory(PROM PLD)

EXAMPLE 1:Implement the following Boolean functions using a

suitable PROM PLD.
f1(a, b, c)=Ʃm(0, 1, 3, 5, 7)
f2(a, b, c)=Ʃm(2, 4, 6, 7)
There are 3 inputs.
➔ 3 INVERTERS and 8 AND gates.
2 output Boolean expressions.
➔2 OR gates.

➔The suitable PROM PLD is 8X2

DIGITAL ELECTRONICS
Programmable Read Only Memory(PROM PLD)

Implementation Diagram:
 DIGITAL ELECTRONICS
Programmable Read Only Memory(PROM PLD)
EXAMPLE 2:Using the smallest size PROM PLD, realize the
following arithmetic Expression;
y(x)=2x+3; 0<x<7; x and y(x) both are in binary.
There are 8 values of x varying from 0 to 7.

➔ There are 3 inputs.

➔For x=7; y(7)=2*7+3=14+3=17.
For expressing 17 in binary form, we require 5 bits.
Hence we require 5 OR gates.
➔3 inverters, 8 AND gates.
DIGITAL ELECTRONICS
Programmable Read Only Memory(PROM PLD)
Truth table for the given expression
y(x)=2x+3.

X2 X1 X0 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 1 1
0 0 1 0 0 1 0 1
0 1 0 0 0 1 1 1
0 1 1 0 1 0 0 1
1 0 0 0 1 0 1 1
1 0 1 0 1 1 0 1
1 1 0 0 1 1 1 1
1 1 1 1 0 0 0 1
 DIGITAL ELECTRONICS
Programmable Read Only Memory(PROM PLD)
Writing the output equations
y0=1;
y1=Ʃm(0, 2, 4, 6);
y2=Ʃm(1, 2, 5, 6);
y3=Ʃm(3, 4, 5, 6);
y4=Ʃm(7);
➔We require 8 * 5 PLD.
➔In the question, since they have mentioned the smallest size
PROM PLD,
by seeing the output equations, we observe that y0=1.
→ Hence , 8*4 PROM PLD is required.
DIGITAL ELECTRONICS
Programmable Read Only Memory(PROM PLD)

Implementation Diagram:
 DIGITAL ELECTRONICS
Programmable Read Only Memory(PROM PLD)
EXAMPLE 3:
y(x)=x2 + 3; where 0<x<3 using 4 * 3 PROM PLD where x and
y(x) are in binary.

B1 B0 Y3 Y2 Y1 Y0

0 0 0 0 1 1
0 1 0 1 0 0
1 0 0 1 1 1
1 1 1 1 0 0
 DIGITAL ELECTRONICS
Programmable Read Only Memory(PROM PLD)

Writing the output equations

y0=Ʃm(0, 2)
y1=Ʃm(0, 2)
y2=Ʃm(1, 2, 3)
y3=Ʃm(3)
DIGITAL ELECTRONICS
Programmable Read Only Memory(PROM PLD)

Implementation Diagram:
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@[Link]
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Combinational Logic Modules

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS
Programmable Array Logic(PALs)

In this type of PLD , OR is fixed –AND is programmable.

Note that there should be maximum 3 inputs to OR gate.

Steps to implement:
1. Draw K-Maps for the given Boolean expression and express
the output equation .
2. Connect the min-terms obtained as the input to AND gates
by marking with X .
3. Put corresponding to the inputs of OR gate.
DIGITAL ELECTRONICS
Programmable Array Logic(PALs)

Implement the following Boolean Expression using 4 input, 3

output PAL PLD.
f1(a, b, c)=Ʃm(0, 3, 5, 6, 7)
f2(a, b, c)=Ʃm(1, 2, 3, 5, 7)

➔f1=a’b’c’+bc+ac+ab where f3=ac+ab

 DIGITAL ELECTRONICS
Programmable Array Logic(PALs)

➔f2=c+a’b
 DIGITAL ELECTRONICS
Programmable Array Logic(PALs)

Implementation Diagram:
 DIGITAL ELECTRONICS
Programmable Array Logic(PALs)

Implement the following Boolean expressions using 4 output, 3 input PAL

PLD.
f1(a, b, c)=Ʃm(1, 2, 4, 6, 7)
f2(a, b, c)=Ʃm( 2, 4, 5, 6)
f3(a, b, c)=Ʃm(1, 4, 6)

f1=a’b’c +ac’+ab+bc’ where f3=a’b’c’+ac’

DIGITAL ELECTRONICS
Programmable Array Logic(PALs)

a bc b’c’ b’c bc bc’

a’ 0 0 0 1
a 1 1 0 1

ab’ bc’

f2=ab’+bc’
DIGITAL ELECTRONICS
Programmable Array Logic(PALs)

a bc b’c’ b’c bc bc’

a’ 0 11 0 0
a 1 0 0 1

ac’ a’b’c

f3=a’b’c’ + ac’
 DIGITAL ELECTRONICS
Programmable Array Logic(PALs)

Implementation Diagram:
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@[Link]
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Combinational Logic Modules

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
 DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)

The general structure is n* m* r

There are n inputs→n inverters

m number of AND gates and r number of OR
gates(dependent on the number of Boolean expression)
 DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)

Implement the following Boolean functions using suitable PLA

PLD.
f1(a, b, c)=Ʃm (1, 2, 3, 7)
f2(a, b,, c)=Ʃm (1 ,5, 7)
DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)
 DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)

f1=a’b’c + a’b + bc

f2=a’b’c + ac

There are 3 INVERTERS, 4 AND gates and 2 OR gates.

→3 * 4* 2 PLA PLD.
 DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)

Implementation Diagram:
 DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)
Implement the following Boolean functions using suitable PLA PLD.
f1(a, b, c)=Ʃm(1, 3, 6, 7)
f2(a, b, c)=Ʃm(0, 3, 4)

a bc b’c’ b’c bc bc’

a’ 0 1 1 0
a 0 0 1 1

a’c ab

f1=a’c+ab
 DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)

f2=a’bc+b’c’
DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)
Implementation Diagram:
 DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)
PLA PLD with complemented outputs:
❖This is done to minimize the number of product terms so that
smallest available PLA can be used to implement the logic.
Steps
❖Find out the logic which provides the fewer product
terms.(whether true or complemented form)
❖Draw the PLA table.
❖Draw the structural diagram.
❖An EXOR array is used after the output of OR gates.
❖If there is non –complemented/true output, then one of two
inputs of the XOR gate is connected to ground and vice versa.
 DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)

While writing the PLA table

1. The variables absent in the product terms are denoted by ‘—’.

2. The variables in product terms with complemented form are

denoted by ‘0’.

3. The variables in true form present in the product term are

denoted by ‘1’.

4. If the boolean expression is implemented in either true or

complemented form,corresponding ones are marked with ‘1 ‘.
 DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)
1. f1(a, b, c)=Ʃm(0, 1, 2, 4)
f2(a, b, c)=Ʃm(0, 5, 6, 7)

a bc b’c’ b’c bc bc’

a’ 11 1 0 11
a 1 0 0 0
b’c’ a’b’ a’c’

f1= b’c’+a’b’+a’c’
f1’=bc+ab+ac
DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)

f2=a’b’c’+ac+ab
f2’=abc+a’c’+a’b’
 DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)

PLA TABLE:

PRODUCT INPUTS OUTPUT

TERMS a b c C T
f1 f2
a’b’c’ 0 0 0 --- 1
ab 1 1 -- 1 1
ac 1 -- 1 1 1
bc -- 1 1 1 --
DIGITAL ELECTRONICS
Programmable Logic Array(PLAs)
Implementation Diagram:
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@[Link]
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS

GAYATHRI DEVI B

Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS

Combinational Logic Modules

GAYATHRI DEVI B
Department of Electrical & Electronics Engineering
DIGITAL ELECTRONICS
Summary of Unit 2

Topics Covered:
1. ADDERS
2. CARRY LOOK AHEAD ADDERS
3. DECIMAL ADDERS
4. COMPARATORS
5. ENCODERS
6. DECODERS
7. MULTIPLEXERS
8. PLDS
 DIGITAL ELECTRONICS
Summary of Unit 2
Serial Adder
A serial adder is used to add two binary numbers in serial form.
The two binary numbers to be added serially are stored in two
shift registers. The circuit adds one pair at a time with the help of
one full adder. The carry output from the full adder is applied to a
D flip-flop, the output of which is then used as a carry input for
the next pair of significant bits. However the sum bit S from the
output of the full adder can be transferred into a third shift
register.
Parallel Adder
A parallel adder is a combinational digital circuit that adds two
binary numbers in parallel form. It consists of full adders
connected in cascade, with the output carry from each full adder
connected to the input carry of the next full adder.
 DIGITAL ELECTRONICS
Summary of Unit 2

Carry Look-ahead Adder

A carry look-ahead adder reduces the propagation delay by

introducing more complex hardware. In this design, the ripple
carry design is suitably transformed such that the carry logic over
fixed groups of bits of the adder is reduced to two-level logic.
DIGITAL ELECTRONICS
Summary of Unit 2

BCD Adder in Digital Logic

BCD stand for binary coded decimal. Suppose, we have two 4-bit
numbers A and B. The value of A and B can varies from 0(0000 in
binary) to 9(1001 in binary) because we are considering decimal
numbers.
The output will varies from 0 to 18, if we are not considering the
carry from the previous sum. But if we are considering the carry,
then the maximum value of output will be 19 (i.e. 9+9+1 = 19).
When we are simply adding A and B, then we get the binary sum.
Here, to get the output in BCD form, we will use BCD Adder.
DIGITAL ELECTRONICS
Summary of Unit 2
Applications of Comparators

[Link] are used in central processing units (CPUs) and

microcontrollers (MCUs).
[Link] are used in control applications in which the binary
numbers representing physical variables such as temperature,
position, etc. are compared with a reference value.
[Link] are also used as process controllers and for Servo
motor control.
[Link] in password verification and biometric applications.
DIGITAL ELECTRONICS
Summary of Unit 2

Binary code of N digits can be used to store 2N distinct elements

of coded information. This is what encoders and decoders are
used for. Encoders convert 2N lines of input into a code of N bits
and Decoders decode the N bits into 2N lines.
Encoders
An encoder is a combinational circuit that converts binary
information in the form of a 2N input lines into N output lines,
which represent N bit code for the input. For simple encoders, it
is assumed that only one input line is active at a time.
As an example, let’s consider Octal to Binary encoder. As shown
in the following figure, an octal-to-binary encoder takes 8 input
lines and generates 3 output lines.
 DIGITAL ELECTRONICS
Summary of Unit 2

DECODERS

In Digital Electronics, discrete quantities of information are

represented by binary codes. A binary code of n bits is capable of
representing up to 2^n distinct elements of coded information.
The name “Decoder” means to translate or decode coded
information from one format into another, so a digital decoder
transforms a set of digital input signals into an equivalent
decimal code at its output. A decoder is a combinational
circuit that converts binary information from n input lines to a
maximum of 2^n unique output lines.
DIGITAL ELECTRONICS
Summary of Unit 2

Multiplexers in Digital Logic

It is a combinational circuit which have many data inputs and
single output depending on control or select inputs. For N input
lines, log n (base2) selection lines, or we can say that for
2n input lines, n selection lines are required. Multiplexers are
also known as “Data n selector, parallel to serial convertor,
many to one circuit, universal logic circuit​”.

Multiplexers are mainly used to increase amount of the data

that can be sent over the network within certain amount of
time and bandwidth.
DIGITAL ELECTRONICS
Summary of Unit 2
Programmable Logic Devices PLDsPLDs are the integrated
circuits. They contain an array of AND gates & another array of
OR gates. There are three kinds of PLDs based on the type of
arrayss, which has programmable feature.
•Programmable Read Only Memory
•Programmable Array Logic
•Programmable Logic Array

Programmable Read Only Memory

DIGITAL ELECTRONICS
Summary of Unit 2

Programmable Array Logic

Programmable Logic Array

DIGITAL ELECTRONICS
Summary of Unit 2

Advantages of Programmable Logic Devices:

Programmable logic devices offer a number of important
advantages over fixed logic devices, including:
1. Design Flexibility: PLDs offer customers much more flexibility
during the design cycle because design iterations are simply a
matter of changing the programming file, and the results of
design changes can be seen immediately in working parts.
[Link]:Lower power plus fewer interconnections
and packages translate into greatly improved system reliability.
3. Lower Power: CMOS and fewer packages combine to reduce
power consumption.
DIGITAL ELECTRONICS
Summary of Unit 2

4. Lower Power: CMOS and fewer packages combine to reduce

power consumption.
5. Reduced complexity: Since PLDs consume lower power
requirements less board space simpler testing procedures.
6. PLDs are field-programmable i. e. can be programmed
outside of the manufacturing environment
7. PLDs are erasable and reprogrammable i.e allows updating a
device or correction of errors and allows to reuse the device for
a different design – the ultimate in reusability!
THANK YOU

Gayathri Devi B
Department of Electrical & Electronics Engineering
gayathridb@[Link]
+91 80 6666 3333 Extn 273