-- This is a simple VHDL code used in EEEB161 video tutorial.

--Library declaration
library ieee;
use ieee.std_logic_1164.all;

-- Input and Output Ports declaration

entity lab2_kp is
port (
a,b,c,d :in std_logic; --Mux input
y1,y2 :out std_logic --Mux output

);
end lab2_kp;

--Function of lab2_kp
architecture func_lab2 of lab2_kp is
begin
y1<= a xor b xor c;
y2<= (a nand b) or ((not c) and d);
end func_lab2;