ELL201

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• Quiz on 16th September 2021
• Minor Exam on 23rd September 2021

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ELL 201: Digital Electronics

Lecture 10

Prof. Manan Suri (EE)

manansuri@ee.iitd.ac.in
http://web.iitd.ac.in/~manansuri/

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Q.) If AND/OR Gate propagation delay = 1ns; XOR gate delay = 2ns
Calculate the full delay time for a 4 bit RCA ?
Solution:

C3 → 8 C2 → 6 C1 → 4

Tand,1

Txor,2 Txor,2 Txor,2 Txor,2 Ans:

10 ns
8+Tand
6+Tand 4+Tand For
=7 =5
=9 both C
8+Txor 6+Txor 4+Txor and S
= 10 Txor+Txor
=8 =6
Txor+Ta =4
9+Tor 7+Tor 5+Tor
= 10 nd+Tor
=8 =6 =4

S3 →10 S2 → 8 S1 → 6 S0 → 4
C4 → 10 C3 → 8 C2 → 6 C1 → 4
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Recap: How to Overcome Flaws of the Ripple-Carry Adder?
Solution – Build a “Carry-Look Ahead Adder” (CLA) using Half Adders

Pi: Propagate
Gi: Generate
Use this for 4-bit adder

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Recap: Carry Look Ahead Adder (CLA)

+
Hardware to compute the Carry terms? → All in SOP form
So just 2 Gate levels → 1 And, 1 OR

Also
called as
LAG

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Recap: Commercial LAG – SN74182

C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0 GI ; PI

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Recap: 4-bit Carry Lookahead Adder
If AND, OR gate propogation delay = 1ns; XOR gate delay = 2ns

Start with 4
2 ns HA
2 ns
= max(Pi=2,Gi=1)

Feed their Pi
1 + 1 ns and Gi to
LAG block

LAG block
will give Ci
2 ns
Use XOR with Ci
Terms to get S
Compare with 4-bit RCA…
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Recap: 16-bit CLA
Design a 16-bit CLA using HAs, LAGs and perform a delay analysis

C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

GI ; PI

C4 = GI + PIC0
C8 = GII + PIIGI + PIIPIC0
C12 = GIII + PIIIGII + PIIIPIIGI + PIIIPIIPIC0

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Recap: 16-bit CLA (Timing Analysis) max(PI=2+1
=3,GI=2+2)
A12B12 A8B8 A4B4 A0B0

H H H H H H H H H H H H H H H H
A A A A A A A A A A A A A A A A
2 ns 2 ns 2 ns P3G3 P0G0 2 ns
C12 C8 C4
LA Gen LA Gen LA Gen LA Gen
C0
6 ns 6 ns 5 ns
4 ns 4 ns 4 ns 4 ns
C11C10C9 C7C6C5 C3 C2 C1
C15C14C13
8 ns 4 ns
8 ns PIVGIV PIIIGIII 7 ns PIIGII PIGI

LA Gen C0

Is 8 ns the answer?
What about Si ?
Si = Ci XOR Pi
So Total delay = 10 ns
Now compare with 16 – bit RCA?
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Recap: 16-bit CLA (Timing Analysis Summary)

1. First layer of Half Adders → Pi and Gi → 2 ns

2. First Layer of Look Ahead Generators → PI, GI → 4 ns

3. Second Layer of LAG → C8, C12 → 6 ns

4. Back to First Layer of LAG → C9, C10, C11… → 8 ns

5. Final Half Adder (Sum) → Si → 10 ns

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Design a 64-bit CLA ? Using Standard blocks!
What is the most recent standard block you learnt?
→ 16 bit - CLA

Px, gx

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Recap: Design a 64-bit CLAUsing
? Standard blocks!
What is the most recent standard
block you learnt? → 16 bit - CLA

16-bit 16-bit 16-bit 16-bit

CLA CLA CLA CLA

LAG Block

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Recap: Design a 64-bit CLA ?

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Recap: 64-bit CLA Design ?
C =G +PC
What is the first step?
Find expression for carry terms
M. Suri, ELL201, (copyright IITD) "Intended for
4 I I 0
C8 = GII + PIIGI + PIIPIC0
C12 = GIII + PIIIGII + PIIIPIIGI + PIIIPIIPIC0
C16 , C32 , C48…, C60 → ?
C16 = GIV + PIVGIII + PIVPIIIGII + PIVPIIIPIIPIGI + PIVPIIIPIIPIC0
PI2 ; GI2 → 3 LAYERS OF LAG
C16 = GI2 + PI2C0
C32 =
GII2 + PII2GI2 + PII2PI2C0
C48 =
GIII2 + PIII2GII2 + PIII2PII2GI2 + PIII2PII2PI2C0
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Recap: Cost/trade-offs of using CLAs ??
1. Layer-1 of HA → Pi and Gi → 2 ns

2. Layer-1 of LAG→ PI, GI → 4 ns → 16 extra LAG units

= max (PI=3, GI=4)

3. Layer-2 of LAG → PI2, GI2 → 6 ns → 4 extra LAG units

= max (PI2=3+1=4, GI2=4+2=6)
4. Layer-3 of LAG → C32, C48 → 8 ns → 1 extra LAG (21!!)

5. Layer-2 of LAG → C36, C40, C44, C52, C56, … → 10 ns

6. Layer-1 of LAG → C37, C38, C39, C41, C42, C43… → 12 ns

7. Sum → 14 ns
Compare with 64-bit RCA ?

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Tentative Timeline
(Note: timeline may change during the semester without any prior notice → details are only of indicative nature)

Lec. No Date Content

1 Intro + Logistics + Course Policy + Motivation etc
2 Why digital, Number Systems + Conversions etc.
3 Fractional, Complements, Addn, Subtraction
4 Logic Gates, Boolean Algebra, Minterm, Maxterm, SOP, POS
5
KMaps, Minimization, XoR Gate
6
7 XOR Gate, Adders (half/full) + Parity bit circuits + 4-bit adder + subtraction +
8 overflow detection + BCD adder, Ripple Carry, CLA, 4-bit, 16-bit, 64-bit, Timing
9 Analysis, etc.
10
Mux + Decoder + Encoder-1
11
12 Quiz-1 - 16th September
Minor week - 23 september 201 minor exam
13
14
Sequential Logic - Latches. Flip flops, varieties, counters, registers, digital CMOS,
15
Verilog intro
16
17
18 PB Set/Assignment or as per need
Mid Sem Break
19
20 FSM intro, Moore, Mealy, Examples, Conversions etc.
21
22
Memory, Advanced topics, etc.
23
24 Extra/Buffer/Cover-up class/As per need
Major Exam Week
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M. Suri, ELL201, (copyright IITD) "Intended for
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 Going Beyond Adders →

Mux, Encoder, Decoder, DeMux etc.

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Multiplexer (Mux)

M. Suri, ELL201, (copyright IITD) "Intended for

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Multiplexer (Mux)

M. Suri, ELL201, (copyright IITD) "Intended for

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Multiplexer (Mux)

M. Suri, ELL201, (copyright IITD) "Intended for

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Multiplexer (Mux)
2 to 1 line Mux

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Multiplexer (Mux)
2 to 1 line Mux

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Multiplexer (Mux)
2 to 1 line Mux

I0

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Multiplexer (Mux)
2 to 1 line Mux

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Multiplexer (Mux)
2 to 1 line Mux

I1

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Multiplexer (Mux)
2 to 1 line Mux

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Multiplexer (Mux)
4 to 1 line Mux

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Multiplexer (Mux)
4 to 1 line Mux → 2 select lines

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Multiplexer (Mux)
4 to 1 line Mux → 2 select lines

M. Suri, ELL201, (copyright IITD) "Intended for

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Multiplexer (Mux)
4 to 1 line Mux → 2 select lines

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Multiplexer (Mux) – Multiple bit selection
Design a Quadruple 2-to-1 line Mux

M. Suri, ELL201, (copyright IITD) "Intended for

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Multiplexer (Mux) – Multiple bit selection
Design a Quadruple 2-to-1 line Mux

M. Suri, ELL201, (copyright IITD) "Intended for

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Multiplexer (Mux) – Multiple bit selection
Design a Quadruple 2-to-1 line Mux

M. Suri, ELL201, (copyright IITD) "Intended for

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Multiplexer (Mux) – Multiple bit selection
Design a Quadruple 2-to-1 line Mux

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Multiplexer (Mux) – Multiple bit selection
Design a Quadruple 2-to-1 line Mux

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Multiplexer (Mux) – Multiple bit selection
Design a Quadruple 2-to-1 line Mux

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Multiplexer (Mux) – Multiple bit selection
Design a Quadruple 2-to-1 line Mux

M. Suri, ELL201, (copyright IITD) "Intended for

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Multiplexer (Mux) – Multiple bit selection
Quadruple 2-to-1 line
Circuit with Enable

M. Suri, ELL201, (copyright IITD) "Intended for

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Multiplexer (Mux) – Multiple bit selection
Quadruple 2-to-1 line
Circuit with Enable

M. Suri, ELL201, (copyright IITD) "Intended for

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Multiplexer (Mux) – Multiple bit selection
Quadruple 2-to-1 line
Circuit with Enable

M. Suri, ELL201, (copyright IITD) "Intended for

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What’s the Mux Advantage?
What is common in all Mux hardware?

- All have SOP form

- All minterms are covered!

2 to 1 mux

4 to 1 mux

4-bit 2 to 1 mux
M. Suri, ELL201, (copyright IITD) "Intended for
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Mux – Advantage - any Logic function can be realized
1. A very efficient method: For N variable function → use Mux with N-1 lines
2. Connect first n-1 variables to selection inputs of the Mux
3. Last variable of function is used for data inputs of the mux
4. Express all data inputs in terms of last variable, its complement, 0 & 1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – Advantage - any Logic function can be realized
1. A very efficient method: For N variable function → use Mux with N-1 lines
2. Connect first n-1 variables to selection inputs of the Mux
3. Last variable of function is used for data inputs of the mux
4. Express all data inputs in terms of last variable, its complement, 0 & 1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – Advantage - any Logic function can be realized
1. A very efficient method: For N variable function → use Mux with N-1 lines
2. Connect first n-1 variables to selection inputs of the Mux
3. Last variable of function is used for data inputs of the mux
4. Express all data inputs in terms of last variable, its complement, 0 & 1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – Advantage - any Logic function can be realized
1. A very efficient method: For N variable function → use Mux with N-1 lines
2. Connect first n-1 variables to selection inputs of the Mux
3. Last variable of function is used for data inputs of the mux
4. Express all data inputs in terms of last variable, its complement, 0 & 1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – Advantage - any Logic function can be realized
1. A very efficient method: For N variable function → use Mux with N-1 lines
2. Connect first n-1 variables to selection inputs of the Mux
3. Last variable of function is used for data inputs of the mux
4. Express all data inputs in terms of last variable, its complement, 0 & 1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – Advantage - any Logic function can be realized
1. A very efficient method: For N variable function → use Mux with N-1 lines
2. Connect first n-1 variables to selection inputs of the Mux
3. Last variable of function is used for data inputs of the mux
4. Express all data inputs in terms of last variable, its complement, 0 & 1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – Advantage - any Logic function can be realized
1. A very efficient method: For N variable function → use Mux with N-1 lines
2. Connect first n-1 variables to selection inputs of the Mux
3. Last variable of function is used for data inputs of the mux
4. Express all data inputs in terms of last variable, its complement, 0 & 1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – Advantage - any Logic function can be realized
1. A very efficient method: For N variable function → use Mux with N-1 lines
2. Connect first n-1 variables to selection inputs of the Mux
3. Last variable of function is used for data inputs of the mux
4. Express all data inputs in terms of last variable, its complement, 0 & 1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – Advantage - any Logic function can be realized
1. A very efficient method: For N variable function → use Mux with N-1 lines
2. Connect first n-1 variables to selection inputs of the Mux
3. Last variable of function is used for data inputs of the mux
4. Express all data inputs in terms of last variable, its complement, 0 & 1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – Advantage - any Logic function can be realized
1. A very efficient method: For N variable function → use Mux with N-1 lines
2. Connect first n-1 variables to selection inputs of the Mux
3. Last variable of function is used for data inputs of the mux
4. Express all data inputs in terms of last variable, its complement, 0 & 1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – Advantage - any Logic function can be realized
1. A very efficient method: For N variable function → use Mux with N-1 lines
2. Connect first n-1 variables to selection inputs of the Mux
3. Last variable of function is used for data inputs of the mux
4. Express all data inputs in terms of last variable, its complement, 0 & 1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – Advantage - any Logic function can be realized
1. A very efficient method: For N variable function → use Mux with N-1 lines
2. Connect first n-1 variables to selection inputs of the Mux
3. Last variable of function is used for data inputs of the mux
4. Express all data inputs in terms of last variable, its complement, 0 & 1

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
Mux – To realize any Logic function

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"
 Thank you
• Announcements
• Quiz on 16th September 2021
• Minor Exam on 23rd September 2021

M. Suri, ELL201, (copyright IITD) "Intended for

Academic Fair Use Only"