EXPERIMENT NO: 5

1. AIM: To design and implement a logic function F (a,b,c,d)=………… using CMOS

logic.
The function F is as given below
F (A, B, C, D) = Ʃ m (0, 3, 5, 7, 11, 13)

2. Software Requirement: LTSpice XVII

3. Theory: The given logic function to be implemented F (A, B, C, D) = Ʃ m (0, 3, 5,

7, 11, 13)

where numbers inside the braces represent the min-terms of the 4-bit function F.
On simplifying above expression using Karnaugh maps technique, we get the
following simplified expression for the function F:

F = 𝐀 𝐁 𝐂 𝐃 + 𝐁𝐂𝐃 + 𝐀𝐂𝐃 + 𝐁𝐂𝐃

Expressing the function F in terms of NAND gates only (by double complementing
and applying de-morgan), we get another expression for the function F:

F = 𝐀 𝐁 𝐂 𝐃. 𝐁𝐂𝐃. 𝐀𝐂𝐃. 𝐁𝐂𝐃

For the realization of the expression for the function F, we need two 4-input NAND
gates and three 3-input NAND gates. (For obtaining the complements of A, B, C and
D i.e. A’, B’, C’ and D’ respectively, we could use NOT gate or 2-input NAND gate
whose inputs are tied together.
Truth-table for the function F:

INPUTS OUTPUT

A B C D F

0 0 0 0 1

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 1

0 1 1 0 0

0 1 1 1 1

1 0 0 0 0

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 0

1 1 1 1 0
4. Schematic Diagram:

5. Output Waveform:
6. Conclusion:

The given boolean function was evaluated from its min-terms and was implemented
using the NAND logic. The function was then verified from its transient response

7. Precaution:

1. Whenever any modification is done to the schematic, it must be checked and saved.
2. All the model library files must be added before performing the simulation.
3. Directions of input and output ports must be taken care.