VERILOG ASSIGMENT 1

NAME- AJAY KUMAR

ENTRY NO.- 2020MT60867
1- The function, F = ∑ (0,1,2,5,6,8,9,11,13,14, 15 ) needs to be
realized using one 8 to 1 multiplexer, and minimum additional
gates.
Implementation Methodology:
a) Draw truth table for function F.
b) IN 8x1 Multiplexer , we select 3 input lines (B,C,D) and get 8 cases that
are input lines for multiplexer.
c) In coding, I used A,B,C,D as input and F as output. In BCD select lines, B
is MSD and D is LSB so we get 2^3 combinations that handles 8 cases.

TRUTH TABLE
A B C D F
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

CIRCUIT DIAGRAM:
B,C,D are select lines and (1,1,~A,A,0,1,1,A)
respectively are input lines.

VERILOG CODE:
In this Verilog code, we have coded a general 8x1 multiplexer in
module named mux8x1_circuit in which we are giving different
inputs and defining the outputs based on the combination of select
lines. This mux8x1_circuit module is then instantiated in the main
mux8x1 module where we define the inputs i0, i1, i2, i3
appropriately and thus we are getting the corresponding outputs.

VERILOG TESTBENCH:

GKT WAVEFORM:
we can observe this wave form using gkt.

EXP-2-Realize the function F = ∑

(0,1,2,5,6,8,9,11,13,14,15) using two 4 to 1 multiplexer,
and minimum additional gates.
Implementation Methodology:
a)Draw truth table for function F.
b) IN 4x1 Multiplexer , we select 2 input lines (C,D) and get
4 cases that are input lines for multiplexer.
c) We also make use of the active low enable input of the
two 4x1 multiplexer. We keep B as the enable input for
one 4x1 Mux and ~B as the enable input for the other.
This is done because we require only one mux to
function at a time and therefore as B and ~B as enable
inputs we will always have one enable as 1 and thus the
respective mux will not give any input.
d) All 0xx combinations are handled by B=0 and All 1xx
combinations are handled by ~B=0 that is B=1.
e) Let f1 be the output when B=0 and f2 be the output
when B=1 then F=f1 + f2 using or gate.

TRUTH TABLE
 A B C D F
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 0
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1

CIRCUIT DIAGRAM:
VERILOG CODE:
In this code, I coded a general 4x1 multiplexer with
active low enable input in module named MUX in
which we are giving different inputs and defining the
outputs based on the combination of select lines.
This MUX modules are instantiated in the main mux4x1
module to create 2 objects named m1 and m2. (i0=vcc,
i1=~A, i2=A,i3=gnd) The inputs i0, i0,i1,i2 are used for
the m1 multiplexer whose enable input is defined by B
whereas the inputs i3,i0,i0,i2 are used in the other m2
multiplexer whose enable input is defined by ~B.
Subsequently, we get f1 and f2 as outputs from the
two multiplexers and we use the OR gate on these two
to get the final output F.
VERILOG TESTBENCH:

GKT WAVEFORM: