1.

Solution
The truth table for the given 8×1 Multiplexer is as shown:

Select lines Output

W X Y F
0 0 0 0
0 0 1 Ź
0 1 0 Z
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 Ź
1 1 1 1
From the truth table,
F=Ẃ X́ Y Ź + Ẃ X Ý Z + Ẃ X Y +W X Ý Ź +W X Y
F=Ẃ X́ Y Ź + Ẃ X Ý Z + X Y ( Ẃ + W )+W X Ý Ź
F=Ẃ X́ Y Ź + Ẃ X Ý Z + X Y +W X Ý Ź
Minterm expansion:
F=Ẃ X́ Y Ź + Ẃ X Ý Z + Ẃ X Y (Z+ Ź )+ W X Ý Ź+ W X Y (Z + Ź)
F=Ẃ X́ Y Ź + Ẃ X Ý Z + Ẃ X Y Z + Ẃ X Y Ź +W X Ý Ź +W X Y Z +W X Y Ź
Maxterm expansion:
F=( W + X + Ý +Z ) ( W + X́+ Y + Ź ) ( W + X́ + Ý + Ź ) ( W + X́ + Ý + Z ) ( Ẃ + X́ +Y + Z ) ( Ẃ + X́ + Ý + Ź ) ( Ẃ + X́ + Ý +Z )

2. Solution
Given logic function:
F ( A , B ,C , D ) =∑ ( 2,3,4,7,8,12 )
The K-map of given function is as shown:

AB 00 01 11 10
CD
00 1 1
01 1 1
11 1
10 1
The sum of product expression from the K-map is:
F= Á B́ C + Á C D+ B Ć D́+ A Ć D́

Rearranging for 3-level logic circuit,

F= Á C ( B́+ D ) + Ć D́( A+ B)

The 3 level OR-AND-OR logic circuit:

Á
C
B́
F
D
Ć
D́
A

1st level 2nd level 3rd level

3-level NAND only logic circuit:

Á
A+ Ć +( B D́)
C
 B
B́+ D Á C ( B́+ D ) +¿
D́ Ć D́( A+ B)
Ć
D́ C+ D+( Á B́)

Á A+ B

B́

1st level 2nd level 3rd level

3. Solution
Given logic function:
F= Á B́ C + A D́+B D
a. K-map of the given function:
 AB 00 01 11 10
CD
00 1 1
01 1 1
11 1 1 1 1
10 1 1
b. The corresponding logic circuit experiences 1-Hazard type of static hazard.
c. There are 3 static 1-Hazard which are indicated in the above K-map with the dotted
rectangles.
d. Now to express the corresponding circuit as hazard-free circuit, we add the corresponding
expressions (terms represented by dotted rectangles) to the given logic function. Hence the
hazard free logic function is given by,
F= Á B́ C + A D́+B D+ A B Ć+ A B C+ Á C D
A B C D

4. Solution
The given function is
F=2∗X +1= X+ X +1
Here, X = X3X2X1X0 is the unsigned four bit binary number.
 The full adder is an adder that takes three inputs and outputs two results. The first two inputs
are A and B, with the third being an input carry C-IN input. The carry output is labeled C-
OUT, whereas the regular output is labeled S, which stands for SUM.
So, we will input some X to both the input of 4-bit full adder and the carry will be initially
one.

X3 X2 X1 X0

Full C-IN Full C-IN C-IN

Full Full
C-OUT C-OUT C-OUT
Adder Adder Adder Adder C-IN=1

C-OUT = C3 S3 S2 S1 S0

Figure: Full adder circuit for F = 2*X+1

Since X is a 4-bits binary number, four full adders are required to add the each bits. The
rightmost full adder adds the two least significant bit (X 0) while the initial carry of one is
provided in the rightmost adder to compensate for the +1 term in the function. The addition
of two X0 bits and carry C-IN = 1 produces the binary number whose least significant bit is
output at S0 while the most significant bit is the carry output C-OUT of the adder which
becomes the carry-in of the adjacent full adder for the bits X 1. Similar process occurs in all
the full adder and the carry output of the X 3 bits full adder is the most significant bit of the
function F. The output will be F = C3S3S2S1S0.

5. Solution
The 74LS151 Multiplexer is an 8×1 multiplexer having 3 select lines to select 8 input lines to
produce one required output. Hence, we require three multiplexers to convert the 3-bits
binary code into gray code and vice-versa.
a. Binary-to-gray code converter:
Truth table of binary-to-gray converter:

Binary Code Gray Code

B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0

The bits of given binary number will be fed into the supply lines of the MUX. One
multiplexer for each bit of gray code i.e. G2, G1 and G0 is required. For the case of G0 bit,
with B2, B1, B0 at the supply lines, the required output G0 is shown in the “G0 column” of
above truth table. Hence the input I0, I1… I7 should be such that the output bit corresponds
to the input binary number as shown by the circuit diagram of binary to gray converter.
Similarly, for G1 and G2 bits, the corresponding input values I0, I1… I7 for the respective
binary bits B2, B1, B0 are shown in truth table.

0 1

74LS151
G0
MUX
 B2 B1 B0

74LS151
G1
MUX

B2 B1 B0

74LS151 G2
MUX

Figure: Binary-to-gray converter

using 74LSI151 Multiplexer
B2 B1 B0
b) Gray-to binary converter
Truth table of gray-to-binary converter

Gray Code Binary Code

G2 G1 G0 B2 B1 B0
0 0 0 0 0 0
0 0 1 0 0 1
 0 1 1 0 1 0
0 1 0 0 1 1
1 1 0 1 0 0
1 1 1 1 0 1
1 0 1 1 1 0
1 0 0 1 1 1

Similarly for gray-to-binary converter, the bits of gray code G2, G1, G0 will be provided in
the supply lines of all 3 multiplexers with the input values I1, I2… I7 provided by the truth
table. Each multiplexer is used to provide the output for each of the 3 bits of the equivalent
binary number.
The converter circuit for gray to binary converter using 3 74LS151 MUX is shown in the
following figure.

0 1

74LS151
B0
MUX
 G2 G1 G0

B1

G2 G1 G0

B2

Figure: Gray-to-binary converter

using 74LSI151 Multiplexer
G2 G1 G0
6. Solution
a. Binary-to-Gray Converter
Truth table for Binary-to-Gray Converter

Binary Code Gray Code

B2 B1 B0 G2 G1 G0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
 1 0 0 1 1 0
1 0 1 1 1 1
1 1 0 1 0 1
1 1 1 1 0 0
Using K-map for G2:

B2 00 01 11 10
B1B0
0 0 0 0 0
1 1 1 1 1
From the K-map,
G 2=B 2
Using K-map for G1:

B2 00 01 11 10
B1B0
0 0 0 1 1
1 1 1 0 0
From the K-map,
G 1= B´ 2 B 1+ B 2 B´1=B 1⊕ B 2

Using K-map for G0:

B2 00 01 11 10
B1B0
0 0 1 0 1
1 0 1 0 1
From the K-map,
G 0= B´ 1 B 0+ B 1 B´0=B 0 ⊕ B1
Showing these with the help of logic gates,

B2 G2

G1
B1

G0
B0
 Figure: Logic gate of binary-to-gray converter

b. Gray-to-Binary Converter
Truth table for Gray-to-Binary Converter

Gray Code Binary Code

G2 G1 G0 B2 B1 B0
0 0 0 0 0 0
0 0 1 0 0 1
0 1 1 0 1 0
0 1 0 0 1 1
1 1 0 1 0 0
1 1 1 1 0 1
1 0 1 1 1 0
1 0 0 1 1 1

Using K-map for B2:

G2 00 01 11 10
G1G0
0 0 0 0 0
1 1 1 1 1
From the K-map,
B 2=G 2

Using K-map for B1:

G2 00 01 11 10
G1G0
0 0 0 1 1
1 1 1 0 0
From the K-map,
B1=G´ 2G 1+ G2 G1=G1
´ ⊕G 2

Using K-map for B0:

G2 00 01 11 10
G1G0
0 0 1 0 1
1 1 0 1 0
From the K-map,
B 0=G 2 G´ 1 G0+
´ G2
´ G1
´ G 0+G 2G 1G 0+ G´ 2 G1 G´ 0

¿ G´ 1 ( G 2 G´ 0+ G´ 2 G0 ) +G1(G 2 G0+ G2
´ G´ 0)

¿ G´ 1 ( G 2⊕ G 0 ) +G 1(G 2ʘ G 0)
¿ G´ 1 ( G 2⊕ G 0 ) +G 1( G 2⊕
´ G 0)

¿ ( G 2⊕G 1⊕G 0 )

Showing these with the help of logic gates,

G2 B2

B1
G1

B0
G0

Figure: Logic gate of binary-to-gray converter

7. Solution

a) A.B = 0 means either one of A and B is zero or both A and B are equal to zero.

A + B = 1 means either one of A and B is 1 or both A and B are equal to 1.

If variables A, B satisfy both the conditions then they must be compliment to each other.

i.e. B́ . B = 0 and B́+B=1 (since, 1.0 = 0 and 1 + 0 = 1)

So, A=B́

b) X.Y = 0 means either X and Y is zero or both X and Y are zero.

X + Y = 1 means either X and Y is 1 or both X and Y are 1.

If variables X, Y satisfy both the conditions then they must be compliment to each other.

i.e. Y´ .Y = 0, Ý +Y =1

So, X =Ý
8. Solution

Truth table of Exclusive OR (XOR) gate:

Inputs Output
A B Z
0 0 0
0 1 1
1 0 1
1 1 0
From the above truth table, the sum of product Boolean expression is

Z= Á B+ A B́

Corresponding AND-OR circuit:

A
Á B

Z= Á B+ A B́

A B́
B

XOR using NAND gate:

Z= Á B+ A B́

9. Solution
Truth table of Exclusive NOR (XNOR) gate:

Inputs Output
A B Z
0 0 1
0 1 0
1 0 0
1 1 1
From the above truth table, the sum of product Boolean expression is

Z= Á B́+ A B

Corresponding AND-OR circuit:

A Á B́
B

Z= Á B́+ A B
AB

10. Solution

For XNOR gate, the output is true only if both bits are equal. Hence the XNOR function can
be used to assist in comparing bits. The logic expression of XNOR gate is:
Z=PQ+ Ṕ Q́

Where, Z = 1 if P = Q. So, for each bits of P and Q, the XNOR expression can be written as;

Zi =Pi Qi + Ṕi Q́i where , i=1,2,3∧Z i=1 if Pi=Qi

The 3-bit comparator’s truth table is given as;

P2Q2 P1Q1 P0Q0 P<Q P=Q P>Q

P2 > Q 2 - - 0 0 1
P2 = Q 2 P1 > Q 1 - 0 0 1
P2 = Q 2 P1 = Q 1 P0 > Q 0 0 0 1
P2 = Q 2 P1 = Q 1 P0 = Q 0 0 1 0
P2 < Q 2 - - 1 0 0
P2 = Q 2 P1 < Q 1 - 1 0 0
P2 = Q 2 P1 = Q 1 P0 < Q 0 1 0 0
From the truth table it can be observed that to check if the number P = P 2P1P0 is less than Q =
Q2Q1Q0, we need to first compare the most significant bits P 2 and Q2. If P2 < Q2, then P < Q.
However if P2 = Q2 we need to check other bits and the necessary condition for P < Q in these
cases are P2 = Q2 with P1 < Q1 or P2 = Q2, P1 = Q1 but P0 < Q0. So, we need to start comparing
from the most significant bit to the least significant bit. Noticing that Z2 and Z1 will be 1
only when P2 = Q2 and P1 = Q1 respectively, the Boolean expression for this circuit can be
written as:

( P<Q )= Ṕ2 Q 2 +Z 2 Ṕ 1 Q 1 +Z 2 Z 1 Ṕ 0 Q 0

For the case of P2 < Q2, Z2 = 0 and hence 2nd and 3rd terms will be 0. Further, P2 will be 0 and
Q2 will be 1 for P2 < Q2. Hence for the first term to give “true” value, the complement of P 2 is
required and so on.

Logic circuit for P < Q:

P2 Q2 P1 Q1 P0 Q0
 Z2

P <
Q

Z1

11. Solution

TPD for inverters, bubbles, NAND and NOR = 10 ns

TPD for AND, and OR = 20 ns

TPD for XOR = 30 ns

TPD for S0

First level:

There are NAND, NOR and NOT gates in parallel and has the same T PD of 10 ns. Therefore,
for first level (TPD1) is

TPD1 = 10 ns

Second level:

There is an inverter and AND gate with bubble in parallel. The T PD of inverter is 10 ns while
that of AND gate with bubble is 10 + 20 = 30 ns. Hence, the T PD of AND gate with bubble is
greater, the largest propagation delay for this level is TPD2 = 30 ns.

Third level:

XOR gate is present in the third level with TPD of 30 ns. So, in this level, TPD3 = 30 ns.

Hence, TPD for S0 = TPD1 + TPD2 + TPD3 = 10 + 30 + 30 = 70 ns.

TPD for S1:

First level:

There are 2 NAND gates, 2 NOR gates and an inverter in parallel with T PD of 10 ns each.
Therefore, for first level (TPD1) is

TPD1 = 10 ns

Second level:

Second level comprises of an AND gate with a bubble (20 + 10 = 30 ns) and an inverter (T PD
= 10 ns) in parallel with OR gates incorporating bubble (T PD = 20 + 10 = 30 ns). The largest
TPD of this parallel branch is 30 ns which is fed into an AND gate (T PD = 20 ns) in the second
level. Hence, the largest propagation delay of second level is;

TPD2 = 30 + 20 = 50 ns

Third level:

XOR gate is present in the third level with TPD of 30 ns. So, in this level, TPD3 = 30 ns.

Hence, TPD for S0 = TPD1 + TPD2 + TPD3 = 10 + 50 + 30 = 90 ns.

TPD for S2:

First level:

There are 3 NAND gates, 3 NOR gates and an inverter in parallel with T PD of 10 ns each.
Therefore, for first level (TPD1) is

TPD1 = 10 ns

Second level:

Second level comprises of an AND gate with a bubble (20 + 10 = 30 ns) and an inverter (T PD
= 10 ns) in parallel with two OR gates incorporating two and three bubbles. However, since
the bubble are in parallel, the TPD for both OR gates is, TPD = 20 + 10 = 30 ns. The largest TPD
of this parallel branch is 30 ns which is fed into an AND gate (T PD = 20 ns) in the second
level. Hence, the largest propagation delay of second level is;

TPD2 = 30 + 20 = 50 ns

Third level:

XOR gate is present in the third level with TPD of 30 ns. So, in this level, TPD3 = 30 ns.

Hence, TPD for S0 = TPD1 + TPD2 + TPD3 = 10 + 50 + 30 = 90 ns.

TPD for S3:

First level:

There are 4 NAND gates, 4 NOR gates and an inverter in parallel with T PD of 10 ns each.
Therefore, for first level (TPD1) is

TPD1 = 10 ns

Second level:

TPD of AND gate with a bubble = 10 + 20 = 30 ns

TPD of inverter in series with AND gate = 10 + 20 = 30 ns

TPD of OR gate with two/three/four parallel bubbles in series with AND gate = 20 + 10 +20

= 50 ns

Hence, the largest TPD for second level is TPD2 = 50 ns

Third level:
XOR gate is present in the third level with TPD of 30 ns. So, in this level, TPD3 = 30 ns.

Hence, TPD for S0 = TPD1 + TPD2 + TPD3 = 10 + 50 + 30 = 90 ns.

TPD for C4:

First level:

There are 4 NAND gates, 4 NOR gates and an inverter in parallel with T PD of 10 ns each.
Therefore, for first level (TPD1) is

TPD1 = 10 ns

Second level:

TPD of inverter in series with AND gate = 10 + 20 = 30 ns

TPD of OR gate with two/three/four/five parallel bubbles in series with AND gate = 20 + 10
+20 = 50 ns

Hence, the largest TPD for second level is TPD2 = 50 ns

Therefore total TPD for C4 = TPD1 + TPD2 = 10 + 50 = 60 ns

12. Solution

When EN_L is asserted, the circuit illustrated in Figure is incorrect because both sides of the
74×139 are enabled at the same time. As a result, two three-state drivers are enabled to drive
SDATA at the same time, causing problems.
The problem may be rectified by adding an additional inverter to the signal flowing to 1G or
2G, ensuring that only one source is driving SDATA at any one moment.

13. Solution

For the given CMOS circuit in Figure 2, the truth table is given as;

S Z
0 B
1 A
From the truth table,

Z=A S +B Ś

Logic diagram:

A AS

S
Z=A S +B Ś

B B Ś

14. Solution

For the given CMOS circuit in Figure 3, the truth table is given as;

Inputs Output
A B Z
 0 0 0
0 1 1
1 0 1
1 1 0
From the truth table,

Z=( Á B+ A B́ ) =A ⊕ B

Hence, the given CMOS circuit performs the XOR operation between the two inputs A and
B.

Logic gate:

A
Á B

Z= Á B+ A B́

A B́
B

15. Solution

The first method (cascaded structure) is:

Odd Parity=X 0 ⊕ X 1 ⊕ X 2 ⊕ X 3 ⊕ … …⊕ X n

Circuit diagram of first method:

 First Delay
X0

X1
Second Delay

X2

2n−1 Delay

Odd Parity
X2 n

Figure: Circuit diagram of cascaded odd parity structure

Hence for the first method, the single input corresponds to n-1 number of XOR gates delays.

The second method (tree-like structure) is:

Odd parity= ( ( X 0 ⊕ X 1 ) ⊕ ( X 2 ⊕ X 3 ) ) ⊕… ⊕ [ X n ]
[ ]
Circuit diagram of 2nd method is shown in the next page.

When 2n inputs are given, the input-to-output propagation delay for the cascaded structure is
2n – 1 XOR gate delays, as shown in the circuit schematics for both approaches. The tree-like
structure, on the other hand, has just 3 XOR gate delays from input to output for 2 n inputs. As
can be seen, the cascaded structure has the highest worst-case delays, while the tree-like form
has the lowest. As a result, cascaded structures are favored only when a time delay is
necessary, such as in high-speed circuit design; otherwise, tree-like structures are preferred.

First Delay
X0

X1 Second Delay

X2

X3

X4
Figure: Circuit diagram of tree-like odd parity structure