Shane Foster

CS 354-02
Project #1
March 29, 2021

I. 3-input minority function

Description
This function takes 3 inputs and produces 1 output. If there are more 0’s than 1’s among the
input values, then the output is 1. Otherwise, the output is 0.

Truth Table

Inputs Output

x y z F

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 0

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 0
K-map

Gate-level Circuit Diagram

 Verilog Source Code

module minority_function(x,y,z,F)
input x;
input y;
input z;
output F;
assign F = (x&y)|(y&z)|(z&x);
end module

II. Conditional 2-bit Inverter

Description
This function takes three inputs x, y, and z and returns two outputs A and B. If x=0 then A=y
and B=z, if x=1 then A=y' and B=z’.
Verilog Source Code

module conditional_inverter(x, y, F)
input x, y;
output F;
assign F = x? ~ y : y;
endmodule
III. 1-bit Full Adder (Cascading 2 Half Adders)
Description
This full adder is constructed from two half adders by connecting A and B as inputs for the first
half adder, connecting the sum of that to an input for the second half adder, connecting the carry-
in (c_in) to the other input for the second half adder, and then ORing two half adders carry
outputs to produce the final carry output (c_out).

Block Diagram
 Verilog Source Code
module half_adder(A,B,sum,carry);
input A,B;
output sum,carry;

xor(sum,A,B);
and(carry,A,B);
endmodule

module full_adder(A,B,c_in,sum,c_out);
input A,B,c_in;
output sum,c_out;

wire s1,c1,c2;
half_adder HA1(A,B,s1,c1);
half_adder HA2(c_in,s1,sum,c2);
or(c_out,c1,c2);
endmodule

module full_adder_tb;
reg A;
reg B;
reg c_in;
wire sum;
wire c_out;
integer i;

full_adder uut (
.A(A),
.B(B),
.c_in(cin),
.sum(sum),
.c_out(c_out)
);

initial begin
A = 0;
B = 0;
c_in = 0;
end

always @ ( A or B or c_in )
begin
for ( i = 0; i < 8; i = i + 1 )
begin
#10 {A, B, c_in} = i;
$monitor( "%d ns: A + B + c_in = %b + %b + %b = c_out sum = %b %b",
$time, A, B, c_in, c_out, sum );
end
#10 $stop;
end

endmodule
Verilog Output

10 ns: A + B + c_in = 0 + 0 + 0 = c_out sum = 0 0

20 ns: A + B + c_in = 0 + 0 + 1 = c_out sum = 0 1

30 ns: A + B + c_in = 0 + 1 + 0 = c_out sum = 0 1

40 ns: A + B + c_in = 0 + 1 + 1 = c_out sum = 1 0

50 ns: A + B + c_in = 1 + 0 + 0 = c_out sum = 0 1

60 ns: A + B + c_in = 1 + 0 + 1 = c_out sum = 1 0

70 ns: A + B + c_in = 1 + 1 + 0 = c_out sum = 1 0

80 ns: A + B + c_in = 1 + 1 + 1 = c_out sum = 1 1

IV. 1-bit Full Adder (Direct Implementation)

Description
A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of 3
inputs: A and B, which represent the two significant bits to be added, and c_in which represents
the carry-in from the previous significant position. It has two outputs: sum which is the
arithmetic sum of A and B which can range from 0-3 and c_out to carry the value in case the
output of sum is 2 or 3, whose binary representation require two digits.
Truth Table

Inputs Outputs

A B C_in Sum C_out

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 1 1

1 1 1 1 1

K-maps
 Gate-level Circuit Diagram (2-Level NAND Logic)

module full_adder (
input A,
input B,
input c_in,
output sum,
output c_out );

wire w1, w2, w3;

and(w1, A, B);
and(w2, A, B);
and(w3, A, B);
or(c_out, w1, w2, w3);
xor(sum, A, B, c_in);

endmodule

module testbench;
reg A;
reg B;
reg c_in;
wire sum;
wire c_out;

integer i;

SingleStage uut (
.A(A),
Verilog Source Code

Verilog Output

time = 0, CIN =0, A=0, B=0, COUT=0, SUM=0

time = 20, CIN =0, A=0, B=1, COUT=0, SUM=1
time = 40, CIN =0, A=1, B=1, COUT=1, SUM=0
time = 60, CIN =0, A=1, B=0, COUT=0, SUM=1
time = 80, CIN =1, A=1, B=0, COUT=1, SUM=0
time = 100, CIN =1, A=0, B=0, COUT=0, SUM=1
time = 120, CIN =1, A=0, B=1, COUT=1, SUM=0
time = 140, CIN =1, A=1, B=1, COUT=1, SUM=1

V. 4-bit Adder/Subtractor

Description
This 4-bit adder/subtractor is constructed by cascading four 1-bit full adders. When the input M
is 0, the circuit acts as an adder. When the input M is 1, the circuit acts as a subtractor.
Block Diagram
 Verilog Source Code
module half_adder(A, B, sum, c_out);
input A,B;
output sum,c_out;
assign s = A^B;
assign c_out = A & B;
endmodule

module full_adder(A, B, c_in, sum, c_out);

input A, B, c_in;
output sum, c_out;
wire s1,c1,c2;
half_adder HA1(A,B,s1,c1);
half_adder HA2(c_in,s1,s,c2);
or (c_out,c1,c2);
endmodule

module FourBit_AddSub(A, B, c_in, sum, c_out);

input [3:0] A, B;
output [3:0] sum;
output c_out;
input c_in;
wire c1,c2,c3,x0,x1,x2,x3;

xor xora (x0, c_in, B[0]);

full_adder FA1 (A[0], x0, c_in, sum[0], c1);
xor xorb (x1, c_in, B[1]);
full_adder FA2 (A[1], x1, c1, sum[1], c2);
xor xorc (x2, c_in, B[2]);
full_adder FA3 (A[2], x2, c2, sum[2], c3);
xor xorc (x3, c_in, B[3]);
full_adder FA4 (A[3], x3, c3, sum[3], c_out);
endmodule

module FourBit_AddSub_TB;
reg [3:0] A;
reg [3:0] B;
reg c_in;
wire [3:0] sum;
wire c_out;

FourBit_AddSub uut (
.A(A),
.B(B),
.c_in(c_in),
.sum(sum),
.c_out(c_out)
);
reg [8:0] i;

initial begin
for (i = 0; i <= 511; i = i + 1) begin
A[3:0] = i[8:5]; B = i[4:1]; c_in = i[0]; #5;
end
end