1 .

Truth table of full adder

A B CIN S COUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Equations:
S=A xor B xor C
Cout=AB+ CIN(A xor B)

Data flow:
Module fa(S,COUT,A,B,CIN);
output S,COUT;
input A,B,CIN;
assign S=(A^B^C);
assign COUT=(A &B)+CIN(A^B);
endmodule
Gate level implementation:
2. Half Adder
Truth table
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
S=A xor B
C=AB
Gate level Implementation:

Data Flow:
Module ha(S,COUT,A,B);
output S,COUT;
input A,B;
assign S=(A^B);
assign COUT=A &B;
endmodule

3.MUX:
Truth table:
A B Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

Y=(~B & ~A & D0) |(~B & A & D1)| (B & ~A & D2) |(B & A& D3)
Gate level Implementation:
Data flow modelling:
Module mux(Y,A,B,D0,D1,D2,D3);
output Y;
input A,B,D0,D1,D2,D3;
assign Y=(~B & ~A & D0) |(~B & A & D1)| (B & ~A & D2) |(B & A& D3);
endmodule
Using concatinatin operator:
Module mux(Y,A,B,D0,D1,D2,D3);
output Y;
input A,B,D0,D1,D2,D3;
assign Y=B?(A?D3:D2):(A?D1:D0);
endmodule

4.Behavioral Modelling
module gate2_module(c,a,b);
input a,b;
output reg c;
always @(a or b)
begin
if (a==1'b1 && b==1'b1)
c=1'b1;
else
 c=1'b0;
end
endmodule

module gate3_module(c,a,b);
input a,b;
output reg c;
always @(a or b)
begin
case({a,b})
2'b11:c=1'b1
default:c=1'b0
endcase
end
endmodule

4-bit magnitude:
Test bench:
// Code your testbench here
// or browse Examples
module tb_magnitude;
 reg [0:3]a,b;
wire gt,lt,eq;
magnitude dut (a,b,gt,lt,eq);
initial
begin
a=4'b0000;b=4'b0001;
#2 a=4'b0001;b=4'b1011;
#2 a=4'b1001;b=4'b0101;
#2 a=4'b1000;b=4'b1000;
#10 $finish;
end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1,tb_magnitude);
$monitor("time=%t A=%4b B=%4b gt=%4b lt=%4b eq=%4b",
$time,a,b,gt,lt,eq);
end
endmodule

design:
module magnitude(a,b,gt,lt,eq);
input [0:3]a,b;
output reg gt,lt,eq;
always@(a,b)
begin
 if(a>b)
begin
gt=1;
lt=0;
eq=0;
end
else if(a<b)
begin
gt=0;
lt=1;
eq=0;
end
else
begin
gt=0;
lt=0;
eq=1;
end
end
endmodule

1*4 mux:
Design:
module mux_1x4 (d,a,b,y);
input [3:0]d;
input a, b;
output reg y;
always @ (*)
begin
case (a | b)
2'b00 : y = d[0];
2'b01 : y = d[1];
2'b10 : y = d[2];
2'b11 : y = d[3];
endcase
end
endmodule

test bench:
module tb();
reg [3:0]d;
reg a,b;
wire y;
mux_1x4 tb(d,a,b,y);
initial
begin

a=1'b0;b=1'b0;d=4'b1010;
#5 a=1'b0;b=1'b1;d=4'b1000;
#5 a=1'b1;b=1'b0;d=4'b1011;
#5 a=1'b1;b=1'b1;d=4'b0000;
#20 $finish;
 end
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1,tb);
$monitor("time=%t| a=%b | b=%b | d=%b | output=%b",$time,a,b,d,y);
end
endmodule