Datapath Logic

Adders and Multipliers

Half Adder
 Modelling of Half Adder

//Gate Level Modeling

module half_adder(a,b,s,c);
input a,b;
//Dataflow Modeling
output s,c; module half_adder(a,b,s,c);
xor (s,a,b); input a,b;
and (c,a,b); output s,c;
assign s= a ^ b;
endmodule
assign c = a & b;
endmodule
Modelling of Half Adder
//Test bench
module half_adder_test();
reg a,b;
wire s,c;
half_adder h1(.a(a),.b(b),.s(s),.c(c));
initial
begin
$monitor ($time“The value of a=%b b=%b s=%b c=%b”, a,b,s,c);
#10 a=1’b0; b=1’b0;
#10 a=1’b0; b=1’b1;
#10 a=1’b1; b=1’b0;
#10 a=1’b1; b=1’b1;
end
endmodule
Full Adder
Full Adder
Full Adder
 Modelling of full adder Circuit – Primitive Instantiation

//Gate Level Modeling

module full_adder(a,b,cin,s,co);
input a,b,cin;
output s,co;
wire s,co,w1,w2,w3;
xor (w1,a,b);
xor (s,w1,cin);
and (w2,w1,cin);
and (w3,a,b);
or (co,w2,w3);
endmodule
 Modelling of full adder Circuit – Continuous Assignment

//Dataflow Modeling
module full_adder(a,b,cin,s,co);
input a,b,cin;
output s,co;
assign s= a ^ b ^ cin;
assign co = (a&b)|(b&cin)|(cin&a);
endmodule
 Modelling of full adder Circuit – Module Instantiation
//Dataflow Modeling
module half_adder(a,b,s,c);
input a,b;
output s,c;
assign s= a ^ b;
assign c = a & b;
//Structural Modeling endmodule
module full_adder(a,b,cin,s,co);
input a,b,cin;
output s,co;
wire s,co,w1,w2,w3;
half_adder h1(.a(a),.b(b),.s(w1),.c(w2));
half_adder h2(.a(w1),.b(cin),.s(s),.c(w3);
or (co,w2,w3);
endmodule
 Modelling of full adder Circuit – Test Bench
module fulladder_tb();
reg a,b,cin;
wire s,co;
full_adder DUT (.a(a),.b(b),.cin(cin),.s(s),.co(co));
integer k;
initial
begin
$monitor ($time,"The Value of a=%b,b=%b,cin=%b,s=%b co=%b",a,b,cin,s,co);
{a,b,cin} = 3’b0;
for (k=0; k<=7; k=k+1)
#5 {a,b,cin} = k;
#20 $stop;
end
endmodule
 Parallel Adder

A S

N-bit Parallel
Adder
B C
 Ripple Carry Adder

• To design an n-bit parallel adder, cascade n full adders.

• Carry output from stage k propagates as carry input to stage k+1

• Carry ripples through all the stages

 Ripple Carry Adder - Delay

• Delay of stage C1=2d • Delay of stage S0 =3d

• Delay of stage C2 =4d • Delay of stage S1 = 2d + 3d
• Delay of stage Cn-1 = 2 (n-1)d • Delay of stage S2 = 4d + 3d
• Delay of stage Cn=2nd • Delay of stage Sn-1=2(n-1)d + 3d = (2n+1)d
Modeling a 4-bit Ripple Carry Adder using Structural Level
 Modeling a 4-bit Ripple Carry Adder using Structural Level
module full_adder (a,b,cin,s,co);
input a,b,cin;
output s,co;
assign s= a ^ b ^ cin;
assign co = (a&b)|(b&cin)|(cin&a);
endmodule

module four_adder(a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire c1,c2,c3;
full_adder fa0 (.a(a[0]),.b(b[0]),.cin(cin), .s(sum[0]),.co(c1));
full_adder fa1 (.a(a[1]),.b(b[1]),.cin(c1), .s(sum[1]),.co(c2));
full_adder fa2 (.a(a[2]),.b(b[2]),.cin(c2), .s(sum[2]),.co(c3));
full_adder fa3 (.a(a[3]),.b(b[3]),.cin(c3), .s(sum[3]),.co(cout));
endmodule
Modeling a 4-bit Ripple Carry Adder using Structural Level
module fulladder_4tb();
reg [3:0] a,b;
reg cin;
wire [3:0]sum;
wire cout;
four_adder DUT (.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout));
integer k;
initial
begin
cin=1'b0;
$monitor ($time,"The Value of a=%b,b=%b,cin=%b,sum=%b cout=%b",a,b,cin,sum,cout);

for (k=0; k<=15; k=k+1)

begin
#5 a = k;
#5 b = k;
end
#20 $stop;
end
endmodule
 Ripple Carry Adder

• Total delay is proportional to the number of bits n.

• Performance degradation for large values of n
• The main bottleneck is the carry, which propagates sequentially from
one stage to the next.
 Carry Look Ahead Adder

• Predict the carry before it’s calculated in each stage

• Generate the carry signals for the various stages in parallel
• Time complexity reduced (Time for computation is constant for n-bit)
• Hardware complexity is more
 Carry Look Ahead Adder

Ai S
• Consider ith
stage in the addition process Full
Bi
• Carry Generate: Adder
Ci Ci+1
• Gi = Ai.Bi
• Carry Propagate
• Pi = Ai exor Bi
• Gi = 1 represents the condition when a carry is
generated in stage i independent of other stages
• Pi =1 represents the condition when an input
carry Ci propagated to the output carry Ci+1
Ci+1= Gi +Pi Ci
 4- bit Carry Look Ahead Adder

C4 = G3+ G2P3+G1P2P3+G0P1P2P3+C0P0P1P2P3
C3 = G2+ G1P2+G0P1P2+C0P0P1P2
C2 = G1+ G0P1+C0P0P1
C1 = G0+ C0P0

S0 = A0 ^ B0 ^C0 = P0 ^ C0
S1 = P1 ^ C1
S2 = P2 ^ C2
S3 = P3 ^ C3
Modeling a 4-bit Ripple Carry Adder using Structural Level
4- bit Carry Look Ahead Adder
module CLA_Adder(a,b,cin,sum,cout);
input[3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire p0,p1,p2,p3,g0,g1,g2,g3,c0,c1,c2,c3,c4;

assign c0=cin,
c1=g0|(p0&cin),
assign p0=(a[0]^b[0]), c2=g1|(p1&g0)|(p1&p0&cin),
p1=(a[1]^b[1]), c3=g2|(p2&g1)|(p2&p1&g0)|(p1&p1&p0&cin),
p2=(a[2]^b[2]), c4=g3|(p3&g2)|(p3&p2&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&cin);
p3=(a[3]^b[3]);

assign sum[0]=p0^c0,
assign g0=(a[0]&b[0]), sum[1]=p1^c1,
g1=(a[1]&b[1]), sum[2]=p2^c2,
g2=(a[2]&b[2]), sum[3]=p3^c3;
g3=(a[3]&b[3]); assign cout=c4;
endmodule