Experiment - 3 Design and Simulation of Four-Bit Ripple Carry Adder

Date:30.07.
2020 19BEC1360
Denny Chellappa
Experiment – 3
Design and simulation of Four-Bit Ripple
Carry Adder
Aim:
To design and simulate the four-bit ripple carry adder using Verilog simulator in
EDA Playground online tool.
a. Design and Implement Basic Logic Gate using gate-level, behavorial, and
dataflow modeling techniques.
b. Instantiate a full adder four times and build a 4-bit ripple-carry adder.
Software used:
EDA playground online tool with Epwave enabled.
Procedure:
1. Open the EDA playground online tool.
2. In the tools & simulators dropdown, select Icarus Verilog 0.9.7.
3. In the design window, type your design Verilog code.
4. In the test bench window, type your testbench Verilog code and run.
5. Select the option “open EPWave after run” on the left side of the tool webpage.
6. Observe the log windows to check for the warnings and errors.
7. If no errors are found, verify the output from the logs.
8. Once the simulation is successful, the EPWave windows pop up, Here verify the
logics using timing diagrams.
Task 1
To Design and Implement Basic Logic Gate using gate-level, behavorial, and dataflow
modeling techniques
1. AND Gate:
Design:
module andgate(a,b,c);
input a,b;
output reg c;
// Structural modelling
and(c,a,b);
//Dataflow modelling
assign c=a&b;
//Behavioural modelling
always @(a or b)begin
if(a==1'b1 & b==1'b1)begin
c=1'b1;
end
else
c=1'b0;
end
endmodule
Testbench:
module andgate_tb;
reg a,b;
wire c;
andgate dut(a,b,c);
initial
begin
$dumpfile("dump.vcd");
$dumpvars();
#5;a=1'b0; b=1'b0;
$monitor($time,"a=%b,b=%b,c=%b",a,b,c);
#5;a=1'b0; b=1'b1;
#5;a=1'b1; b=1'b0;
#5;a=1'b1; b=1'b1;
#5; $finish;
end
endmodule
Log Window:
VCD info: dumpfile dump.vcd opened for output.

5a=0,b=0,c=0
10a=0,b=1,c=0
15a=1,b=0,c=0
20a=1,b=1,c=1
Finding VCD file...
./dump.vcd
EPWave Window:
2. OR Gate
Design:
module orgate(a,b,c);
input a,b;
output reg c;
or(c,a,b);
assign c=a|b;
c=1'b0;
end
else
c=1'b1;
endendmodule
Testbench:
module orgate_tb;
reg a,b;
wire c;
orgate dut(a,b,c);
initial
begin
$dumpvars();
#5;a=1'b0; b=1'b0;
#5;a=1'b0; b=1'b1;
#5;a=1'b1; b=1'b0;
#5;a=1'b1; b=1'b1;
#5; $finish;
end
endmodule
Log Window:
5a=0,b=0,c=0
10a=0,b=1,c=1
15a=1,b=0,c=1
20a=1,b=1,c=1
Finding VCD file...
./dump.vcd
EPWave Window:
3. NOT Gate
Design:
module notgate(a,b,c);
input a;
output reg c;
not(c,a);
assign c=~a;
always @(a)begin
Testbench:
module notgate_tb;
reg a;
wire c;
notgate dut(a,b,c);
initial
begin
$dumpvars();
#5;a=1'b0;
if(a==1'b1)begin
c=1'b0;
end
else
c=1'b1;
end
endmodule
$monitor($time,"a=%b,c=%b",a,c);
#5;a=1'b0;
$monitor($time,"a=%b, c=%b",a,c);
#5;a=1'b1;
#5;a=1'b1;
#5; $finish;
end
endmodule
Log Window:
5a=0,c=1
10a=0,c=1
15a=1,c=0
20a=1,c=0
Finding VCD file...
./dump.vcd
EPWave Window:
4. NAND Gate
Design:
module nandgate(a,b,c);
input a,b;
output reg c;
nand(c,a,b);
assign c=1~(a&b);
c=1'b0;
end
else
c=1'b1;
end
endmodule
Testbench:
module nandgate_tb;
reg a,b;
wire c;
nandgate dut(a,b,c);
initial
begin
$dumpvars();
#5;a=1'b0; b=1'b0;
#5;a=1'b0; b=1'b1;
#5;a=1'b1; b=1'b0;
#5;a=1'b1; b=1'b1;
#5; $finish;
end
endmodule
Log Window:
5a=0,b=0,c=1
10a=0,b=1,c=1
15a=1,b=0,c=1
20a=1,b=1,c=0
Finding VCD file...
./dump.vcd
EPWave Window:
5. NOR Gate
Design:
module norgate(a,b,c);
input a,b;
output reg c;
nor(c,a,b);
assign c=1~(a|b);
c=1'b1;
end
else
c=1'b0;
end
endmodule
Testbench:
module norgate_tb;
reg a,b;
wire c;
norgate dut(a,b,c);
initial
begin
$dumpvars();
#5;a=1'b0; b=1'b0;
#5;a=1'b0; b=1'b1;
#5;a=1'b1; b=1'b0;
#5;a=1'b1; b=1'b1;
#5; $finish;
end
endmodule
Log Window:
5a=0,b=0,c=1
10a=0,b=1,c=0
15a=1,b=0,c=0
20a=1,b=1,c=0
Finding VCD file...
./dump.vcd
EPWave Window:
6. XOR Gate
Design:
module xorgate(a,b,c);
input a,b;
output reg c;
xor(c,a,b);
assign c=(a^b);
if((a==1'b0 & b==1'b1)|( a==1'b1 & b==1'b0))begin
c=1'b1;
end
else
Testbench:
module xorgate_tb;
reg a,b;
wire c;
xorgate dut(a,b,c);
initial
begin
$dumpvars();
#5;a=1'b0; b=1'b0;
#5;a=1'b0; b=1'b1;
c=1'b0;
end
endmodule
#5;a=1'b1; b=1'b0;
#5;a=1'b1; b=1'b1;
#5; $finish;
end
endmodule
Log Window:
5a=0,b=0,c=0
10a=0,b=1,c=1
15a=1,b=0,c=1
20a=1,b=1,c=0
Finding VCD file...
./dump.vcd
EPWave Window:
7. XNOR Gate
Design:
module xnorgate(a,b,c);
input a,b;
output reg c;
xnor(c,a,b);
Testbench:
module xnorgate_tb;
reg a,b;
wire c;
xnorgate dut(a,b,c);
initial
begin
assign c=~(a^b);
if((a==1'b1 & b==1'b1)|( a==1'b0 & b==1'b0))begin
c=1'b1;
end
else
c=1'b0;
end
endmodule
$dumpvars();
#5;a=1'b0; b=1'b0;
#5;a=1'b0; b=1'b1;
#5;a=1'b1; b=1'b0;
#5;a=1'b1; b=1'b1;
#5; $finish;
end
endmodule
Log Window:
5a=0,b=0,c=1
10a=0,b=1,c=0
15a=1,b=0,c=0
20a=1,b=1,c=1
Finding VCD file...
./dump.vcd
EPWave Window:
Task 2
To Instantiate a full adder four times and build a 4-bit ripple-carry adder.
4 Bit Ripple Carry Adder
Design:
module fulladder(S,Cout,A,B,Cin);
input A,B,Cin;
output S,Cout;
wire w1,w2,w3,w4;
xor(w1,A,B);
xor(S,Cin,w1);
and(w2,A,B);
and(w3,A,Cin);
and(w4,B,Cin);
or(Cout,w2,w3,w4);
endmodule
Testbench:
module ripplecarryadder_tb();
wire [3:0] S;
wire C;
reg [3:0] A,B;
wire C1;
wire C2;
wire C3;
fulladder fa_A(S[0],C1,A[0],B[0],0);
fulladder fa_B(S[1],C2,A[1],B[1],C1);
fulladder fa_C(S[2],C3,A[2],B[2],C2);
fulladder fa_D(S[3],C,A[3],B[3],C3);
initial begin
$dumpvars();
#5; A=4'b0101; B=4'b1010;
$monitor($time,"A=%4b,B=%4b,S=%4b,C=%b",A,B,S,C);
#5; $finish;
end
endmodule
Log Window:
5A=0101,B=1010,S=1111,C=0
Finding VCD file...
./dump.vcd
EPWave Window:
Conclusion:
Thus, designed and simulated the four-bit ripple carry adder using Verilog
simulator in EDA Playground online tool.

Experiment - 3 Design and Simulation of Four-Bit Ripple Carry Adder

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Experiment - 3 Design and Simulation of Four-Bit Ripple Carry Adder

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Date:30.07.

VCD info: dumpfile dump.vcd opened for output.

4 Bit Ripple Carry Adder

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