CPE 316 - INTRODUCTION TO HDL

LABORATORY NO. 1
Verilog Model Components

SUBMITTED BY:
RANDY

SUBMITTED TO:
ENGR. YUNEZA CLAIRE Y. MORTOS

SEPTEMBER 2023
Intended Learning Outcomes (ILOs):
The students shall be able to:
1. Learn the software used in Verilog HDL.
2. Simulate the operation used in Verilog HDL.
3. Create appropriate Test Bench for each Verilog code.
4. Transpose the given Verilog code into Logic Gates circuit diagram using Logisim Software
Task Assessment
 Laboratory Activity
 Practical Quiz
Resources:
 Computers with Verilog Simulator
Procedure and Output
1. Open your Verilog simulator if you have it installed on your computer. You can also use the online compiler of
Verilog using this link: https://www.jdoodle.com/execute-verilog-online/
 VERILOG ENVIRONMENT FAMILIARIZATION

Part 1: Installing and Running Verilog

1. Click the link below for the Introduction to Verilog HDL.

http://www.referencedesigner.com/tutorials/verilog/verilog_01.php

2. Click the link to install a compiler / simulator

http://www.referencedesigner.com/tutorials/verilog/verilog_02.php

3. Download the link to install a compiler / simulator. http://bleyer.org/icarus/

4. Click the icon to install the Verilog compiler. See the procedure below:

(a) (b) (c)

Figure 1: Verilog Installation (a) Agreement (b) Create a desktop shortcut (c) Iverilog Directory
 Part 2: Verilog Source Code

1. You can open notepad or notepad++ text editor to type the code. Create a Verilog code by typing the following
code below. OR you can use the online compiler if you do not have the Verilog software installed on your
computer. https://www.jdoodle.com/execute-verilog-online/

module sample_code();
initial begin
$display("Hello World");
$display("I'm the best Computer Engineer!");
$finish;
end
endmodule

Note: Make sure not to use capital letters for the reserved words such as module and endmodule.

Breakdown:
 module sample_code();: This line defines a module called sample_code. A module is like a box where you can
put your code.
 initial begin: This part tells the computer to start doing something when the program begins.
 $display("Hello World");: This line is like a message that the computer will show on the screen. It says "Hello
World."
 $display("I'm the best Computer Engineer!");: This line is another message. It says "I'm the best Computer
Engineer!"
 $finish;: This line tells the computer to stop running the program.
So, when you run this code, it will show those messages on the screen and then stop. It's a simple program to
display messages.

2. Click “Execute” to run the code. If there is no error message, that means that you were able to create and compile
the Verilog code correctly.
 Part 3: Verilog Source Code Logic Gates
AND GATE
1. Refer to the code below, Truth Table AND Gate, type the following code using the compiler.

module AND2input(a,b,c);
input a,b;
output c;
and a1(c,a,b);
endmodule

If we are to synthesize the code above, it is also the same as the figure below:

Breakdown:

 module AND2input(a, b, c);: This line defines a module named AND2input.

 input a, b;: These lines declare that a and b are inputs to this module.
 output c;: This line declares that c is an output of this module.
 and a1(c, a, b);: Here, an AND gate is instantiated and named a1. This AND gate has three wires
connected to it: c, a, and b. The c wire is the output of the AND gate, and a and b are the two inputs to the
AND gate. The AND gate will output c based on the values of a and b

2. Click “Execute.” If there is no error message displayed in the screen, that means your code is compiled correctly.

3. To see how the code works, we need to create a test bench or stimulus. Go back to program. Type the following codes
below the previous one.

module TestBench;
reg a, b;
wire c;

initial begin
$display("time a b c"); // print
a = 0; b = 0;
#1 b = 1; // a = 0 b = 1
#1 a = 1; // a = 1 b = 1
#1 b = 0; // a = 1 b = 0
#1 ;
end

AND2input U1(
.a(a),
.b(b),
.c(c)
);

initial
$monitor("%g a=%b b=%b c=%b", $time, a, b, c);
endmodule
Breakdown:

 module TestBench;: This line defines a module called TestBench. In Verilog, a testbench is used to simulate
and test the functionality of other modules.
 reg a, b;: These lines declare two registers, a and b, which can store binary values (0 or 1). They are used as
inputs to the circuit under test.
 wire c;: This line declares a wire c, which is used to capture the output of the circuit under test.
 initial begin: This is the start of the initial block, which is executed at the beginning of the simulation.
 $display("time a b c");: This line is a display statement that prints a header to the console to label the
columns in the output.
 a = 0; b = 0;: These lines initialize the values of a and b to 0.
 #1 b = 1;: This line delays the simulation by 1 time unit (#1) and then sets the value of b to 1.
 #1 a = 1;: Similarly, this line delays the simulation by 1 time unit, and then sets the value of a to 1.
 #1 b = 0;: This line delays the simulation by 1 time unit and sets the value of b to 0.
 #1 ;: This is an empty delay line that waits for another time unit.
 end: This marks the end of the initial block.
 AND2input U1(.a(a), .b(b), .c(c));: This line instantiates the AND2input module named U1 and connects its
inputs and outputs to the signals a, b, and c defined in the testbench module.
 initial $monitor("%g a=%b b=%b c=%b", $time, a, b, c);: This line sets up a monitoring process that
displays the values of a, b, and c along with the simulation time using the $monitor system task. It
continuously monitors and displays these values during the simulation.

4. Execute the program.

 Part 4: Logic Circuit Diagram using Logisim Software

To verify if the result is accurate, construct the two (2) input AND gate circuit diagram using Logisim Software.
The following links to start with the Logisim software installation:
1. To download the software, click the link below: http://www.cburch.com/logisim/download.html

 This is what the software will look like upon opening.

CANVAS

 In the upper right corner, you will see the following:

 Draw the two (2) inputs, and AND Gate by dragging them onto the canvas.

 Note that by default, the AND gate has 5 inputs. You change the number of inputs by selecting the AND Gate
and changing the “Number of Inputs” to 2 since we only have two inputs. Use the figure below for your
reference.
  After changing the number of inputs to 2, click “Analyze Circuit”

 Click “table” to show the truth table of the circuit.

You can use the Logisim Software to check if your program result is correct in Verilog.
Name: Randy Macapagal Name of the Faculty: Engr. Yuneza Mortos
Course Code /Section: CPE 316- CPE31S3 Date Performed: 07/09/2023

Data and Result:

A. Run the additional logic gate operation to learn the software in Verilog HDL. Simulate
the operation of Logic Gates using Verilog.

Logic Gates Logic Symbol Boolean Expression Logic gate primitive code
F = x’ module NOT2input(a,b,c);
1. NOT Gate input a,b;
output c;
not n1(c,a,b);
endmodule

module TestBench;
reg a, b;
wire c;

initial begin
$display("time a b c"); // print
a = 0; b = 0;
#1 b = 1; // a = 0 b = 1
#1 a = 1; // a = 1 b = 1
#1 b = 0; // a = 1 b = 0
#1 ;
end

NOT2input U1(
.a(a),
.b(b),
.c(c)
);

initial
$monitor("%g a=%b b=%b c=
%b", $time, a, b, c);
endmodule
F=x+y module OR2input(a,b,c);
2. OR gate input a,b;
output c;
or n1(c,a,b);
endmodule

module TestBench;
reg a, b;
wire c;

initial begin
$display("time a b c"); // print
a = 0; b = 0;
#1 b = 1; // a = 0 b = 1
#1 a = 1; // a = 1 b = 1
#1 b = 0; // a = 1 b = 0
 #1 ;
end

OR2input U1(
.a(a),
.b(b),
.c(c)
);

initial
$monitor("%g a=%b b=%b c=
%b", $time, a, b, c);
endmodule
F = xy’ module NAND2input(a,b,c);
3. NAND gate input a,b;
output c;
nand n1(c,a,b);
endmodule

module TestBench;
reg a, b;
wire c;

initial begin
$display("time a b c"); // print
a = 0; b = 0;
#1 b = 1; // a = 0 b = 1
#1 a = 1; // a = 1 b = 1
#1 b = 0; // a = 1 b = 0
#1 ;
end

NAND2input U1(
.a(a),
.b(b),
.c(c)
);

initial
$monitor("%g a=%b b=%b c=
%b", $time, a, b, c);
endmodule
F = (x + y)’ module NOR2input(a,b,c);
4. NOR gate input a,b;
output c;
nor n1(c,a,b);
endmodule

module TestBench;
reg a, b;
wire c;

initial begin
$display("time a b c"); // print
a = 0; b = 0;
 #1 b = 1; // a = 0 b = 1
#1 a = 1; // a = 1 b = 1
#1 b = 0; // a = 1 b = 0
#1 ;
end

NOR2input U1(
.a(a),
.b(b),
.c(c)
);

initial
$monitor("%g a=%b b=%b c=
%b", $time, a, b, c);
endmodule
B. Create appropriate Test Bench for each Verilog code.
Note: To verify if the result is correct, get the truth table of each logic gate.

Logic Gates Logic gate primitive code Testbench Module

module NOT2input(a,b,c);
1. NOT Gate input a,b;
output c;
not n1(c,a,b);
endmodule

module TestBench;
reg a, b;
wire c;

initial begin
$display("time a b c"); // print
a = 0; b = 0;
#1 b = 1; // a = 0 b = 1
#1 a = 1; // a = 1 b = 1
#1 b = 0; // a = 1 b = 0
#1 ;
end

NOT2input U1(
.a(a),
.b(b),
.c(c)
);

initial
$monitor("%g a=%b b=%b c=
%b", $time, a, b, c);
endmodule
module OR2input(a,b,c);
2. OR gate input a,b;
output c;
or n1(c,a,b);
endmodule

module TestBench;
reg a, b;
wire c;

initial begin
$display("time a b c"); // print
a = 0; b = 0;
#1 b = 1; // a = 0 b = 1
#1 a = 1; // a = 1 b = 1
#1 b = 0; // a = 1 b = 0
#1 ;
end

OR2input U1(
.a(a),
 .b(b),
.c(c)
);

initial
$monitor("%g a=%b b=%b c=
%b", $time, a, b, c);
endmodule
module NAND2input(a,b,c);
3. NAND gate input a,b;
output c;
nand n1(c,a,b);
endmodule

module TestBench;
reg a, b;
wire c;

initial begin
$display("time a b c"); // print
a = 0; b = 0;
#1 b = 1; // a = 0 b = 1
#1 a = 1; // a = 1 b = 1
#1 b = 0; // a = 1 b = 0
#1 ;
end

NAND2input U1(
.a(a),
.b(b),
.c(c)
);

initial
$monitor("%g a=%b b=%b c=
%b", $time, a, b, c);
endmodule
module NOR2input(a,b,c);
4. NOR gate input a,b;
output c;
nor n1(c,a,b);
endmodule

module TestBench;
reg a, b;
wire c;

initial begin
$display("time a b c"); // print
a = 0; b = 0;
#1 b = 1; // a = 0 b = 1
#1 a = 1; // a = 1 b = 1
#1 b = 0; // a = 1 b = 0
#1 ;
end
 NOR2input U1(
.a(a),
.b(b),
.c(c)
);

initial
$monitor("%g a=%b b=%b c=
%b", $time, a, b, c);
endmodule
C. Transpose the given Verilog code into Logic Gates circuit diagram using
Logisim Software. Print Screen the result
Logic Gates Truth Table Truth table using Logisim

1. NOT Gate

2. OR gate

3. NAND gate

4. NOR gate