Lecture 3:

Modeling in Verilog
Behavioral Modeling in Verilog
 Behavioral Models : Higher level of modeling where behavior
of logic is modeled.
 This is the very important and popular modeling style. This
modeling style is always preferred among all other modeling
style.
 Verilog behavioral code is inside procedure blocks, but there
is an exception: some behavioral code also exist outside
procedure blocks.
 Procedural Verilog code is like programming in a computer
language—with one large exception: Procedural Verilog code
adds a concept of time.
Example 1: Behavioral 2×1 MUX Verilog Code

1. module mux (OUT, A, B, SEL);

2. output OUT;
3. input A,B,SEL;
4. assign OUT = (SEL) ? B : A;
5. end module
Procedural Blocks
 There are two types of procedural blocks in Verilog:
1) initial : initial blocks execute only once at time zero
(start execution at time zero).
2) always : always blocks loop to execute over and over
again.
Initial Block
 Verilog interprets the initial keyword to mean “start
here at time 0”.
 The keyword initial is used not only for initialization,

but also as a place for starting code.

 The time at which the statements finish depends on the

code in the initial block.

 If you want to do more than one operation in an initial

block, you will need to use a begin-end block or fork-

join block.
Example 2: Initial Block
1. module initial_example();
2. reg clk, reset, enable, data;
3. initial
4. begin
5. clk = 0;
6. reset = 0;
7. enable = 0;
8. data = 0;
9. end
10. endmodule
Always Block
 The always keyword is similar in behavior to the initial
keyword.
 Verilog also begins to run always statements at time 0.
 The difference between initial and always statements is

what happens when the statements finish running.

 The always block starts again when it finishes.
 An always block is like an initial block with an infinite

loop.
Example 3: Always Block
 module always_example();
 reg clk, reset, enable, q_in, data;
 always @ (posedge clk)
 if (reset) begin
 data <= 0;
 end
 else if (enable) begin
 data <= q_in;
 end
 endmodule
Delays
 Every statement in Verilog may have a delay before it
is run. If we have three initial statements as in the
module in Example 3, we know they will all start at
time 0.
 But they must run in some order: Which one will run

first? This will be control by providing delays.

 The “ # ” symbol is the delay operator in Verilog.
Example 4: Delay
 Three Initial Statements without delay
 module three_initial;
 initial $display("Initial Statement 1");
 initial $display("Initial Statement 2");
 initial $display("Initial Statement 3");
 endmodule
 Three Initial Statements with Delay
 module three_initial_with_delay;
 initial #1 $display("Initial Statement 1");
 initial $display("Initial Statement 2");
 initial #2 $display("Initial Statement 3");
 endmodule
Begin-end Block
 The statements in the begin-end block are sequential so
we know the statements will execute in the order you
would expect.
 In begin-end blocks delays are additive.
 Multiple begin-end blocks can be nested.
Example 5: Delay with Begin-end
 Initial (begin-end) Statement without delay
 module initial;
 initial begin
 $display("Initial Statement 1");
 $display("Initial Statement 2");
 $display("Initial Statement 3");
 end
 endmodule
 Initial (begin-end) Statement with Delay
 module initial_with_delay;
 initial begin
 #1 $display("Initial Statement 1");
 $display("Initial Statement 2");
 #2 $display("Initial Statement 3");
 end
 endmodule
Fork-join Block
 The fork-join block is similar to the begin-end block: It
is also used to group statements.
 In fork-join blocks, the statements are concurrent
 Delays are independent, or absolute from the time the

fork-join block starts.

Example 6: fork-join Block
 module initial_fork_join();
 reg clk, reset, enable, data;
 initial
 fork
 #1 clk = 0;
 #10 reset = 0;
 #5 enable = 0;
 #3 data = 0;
 join
 $finish;
 end
Summary
Dataflow Modeling in Verilog
 The design based on equation. At this level, the
module is designed by specifying the data flow.
 The designer is aware of how data flows between

hardware registers and how the data is processed in

the design.
 Keyword assign is used.
 assign c=a+b;
 assign b=~a;
 assign c=a&b;
Gate Level Modeling in Verilog
 The module is implemented in terms of logic gates
and interconnections between these gates.
 Design at this level is similar to describing a design

in terms of a gate-level logic diagram.

 The gates are pre defined in Verilog library.
 Example:
 and a1(output, input);
 or a1(output, input);
 nor a1(output, input);
 xor a1(output, input);
 xnor a1(output, input);
 not a1(output, input);
Gate Level vs Data flow Modeling
 Gate level Dataflow level
 Example:
 module and12(a,b,c); module and12(a,b,c);

 input a,b; input a,b;

 output c; output c;

 and (c,a,b); assign c=a&b;

 endmodule; endmodule;
Switch Level Modeling
 In verilog transistor are also known as switches that
either conduct or open.
 Verilog provide the ability to design at MOS transistor

level.
 Design at this level is becoming rare, due to increasing

complexity of circuits (millions of transistor) and

availability of CAD tools.
 The keywords are nmos, pmos and cmos.
Structural Modeling (Gate Level )
 A circuit is defined by explicitly showing how to
construct it using logic gates, pre defined modules, and
the interconnections between them.
 Structural modeling is similar to drawing a schematic

diagram for the circuit.

 Hand-Designed systems always the most efficient.
 Power, area, frequency requirement can be most

accurately met by designer.

 Structural modeling supports hierarchical style of
modeling
 Modeling in terms of gates. Describing the design in

terms of its structure.

 Hand-Designed systems are always the most efficient.
 Structural elements of a Verilog structural description

are logic gates and user-defined components connected

by wires.
 Structural description can be viewed as a simple netlist

composed of nets that connect instantiations of gates.

 Half Adder
 S=~A.B+A.~B
 C=A.B
 Half Adder using Dataflow
 module halfadder(A,B,S,C);
 input A,B;
 output S,C;
 assign S=A^B;
 assign C=A&B;
 endmodule
Half Adder using Gate Level
 module halfadder_g(A,B,S,C);
 input A,B;
 output S,C;
 xor(S,A,B);
 and(C,A,B);
 endmodule
Full Adder using Structural Modeling
 Sum =A xor B xor Cin
 Cout=A.B+B.C+C.A
 s1

s3
s2
 module fulladder(A,B,C,Sum, Cout);

 input A,B,C;
 output Sum, Cout;
 wire S1,S2,S3;
 Halfadder haa(.A(A),.B(B),.S(S1),.C(S2));
 Halfadder hab(.A(S1),.B(C),.S(Sum),.C(S3));

or (Cout,S3,S2);

 endmodule
2:1 Mux
 module mux21_always(A,B,S0,Z);
 input A,B,S0;
 output Z;
 reg Z;

 always@(A or B or S0)
 if(S0)
 Z=B;
 else
 Z=A;
 endmodule
4:1 Mux using Structural Modeling
t1

t2
 module mux41_struc(I0,I1,I2,I3,S0,S1,Y);
 input I0,I1,I2,I3,S0,S1;
 output Y;
 wire t1,t2;

 mux21_always haa (.A(I0),.B(I1),. S0(S0),. Z(t1));

 mux21_always hab (.A(I2),.B(I3),. S0(S0),. Z(t2));
 mux21_always hac (.A(t1),.B(t2),. S0(S1),. Z(Y));

 endmodule
2:4 using Behavioral Modeling
 module decoder24(a,y);
 Input [1:0] a;
 output [3:0] y;
 reg [3:0] y;
 always@(a)
 begin
 y[3]=a[1]&a[0];
 y[2]=!a[1]&a[0];
 y[1]=a[1]&!a[0];
 y[0]=!a[1]&!a[0];
 end
 endmodule
 D Flip Flop
 module dff(d,clk,reset,q);
 Input d,clk,reset,;
 output q;
 reg q;
 always@(posedge clk)
 begin
 If(reset)
 q<=1’b0;
 else
 q<=d;
 end
 endmodule
Gate

 module gate(a,b,c,d,e,f,y);
 input a,b,c,d,e,f;
 output y;
 wire t1,t2,t3,y;
 nand #1 g2(t1,a,b);
 and #1 g1(t1,c,~b,d);
 nor #2 g3(t2,e,f);
 nand #1 g4(y,t1,t2,t3);
 endmodule
Gate testbench
 module testbench;
 reg a,b,c,d,e,f;
 wire y;
 gate dut(a,b,c,d,e,f,y);
 initial
 begin
 $monitor($time,"a=%b,b=%b,c=%b,d=%b,f=%b,y=%b",a,b,c,d,e,f,y);
 #5 a=1;b=0;c=0;d=1;e=0;f=0;
 #5 a=0;b=0;c=1;d=1;e=0;f=0;
 #5 a=1;c=0;
 #5 f=1;
 #5 $finish;
 end
 endmodule
4 bit ripple carry adder
Full adder using behavioral
 module fulladder_behavioral(s,cy,a,b,c);
 input a,b,c;
 output s,cy;
 assign s=a^b^c;
 assign cy=a&b|b&c|c&a;
 endmodule
4 bit ripple carry adder using
structural
4 bit ripple carry adder using
behavioral
 module ripple_4bitbehav(s,cy,x,y,cin);
 input [3:0]x,y;
 output [3:0]s;
 input cin;
 output cy;
 assign{s,cy}=x+y;
 endmodule
4 bit ripple carry adder using
structural
 module sum(sum,a,b,c);
 input a,b,c;
 wire t;
 output sum;
 xor x1(t,a,b);
 xor x2(sum,t,c);
 endmodule
sum
 module carry(carry,a,b,c);
 input a,b,c;
 output carry;
 wire t1,t2,t3;
 and y1(t1,a,b);
 and y2(t2,b,c);
 and y3(t3,c,a);
 or y4(carry,t1,t2,t3);
 endmodule
 module sum_carry(s,cy,a,b,c);
 input a,b,c;
 output s,cy;
 sum a0(s,a,b,c);
 carry a1(cy,a,b,c);
 endmodule
 module ripple_4bit(s,cy,x,y,cin);
 input [3:0]x,y;
 output [3:0]s;
 input cin;
 wire [2:0]cy_out;
 output cy;
 sum_carry b0(s[0],cy_out[0],x[0],y[0],cin);
 sum_carry b1(s[1],cy_out[1],x[1],y[1],cy_out[0]);
 sum_carry b2(s[2],cy_out[2],x[2],y[2],cy_out[1]);
 sum_carry b3(s[3],cy,x[3],y[3],cy_out[2]);
 endmodule
16 bit adder using behavioral
 module bit16_behav(x,y,z,cy,zr,s,p,ov);
 input [15:0]x,y;
 output[15:0]z;
 output cy,z,s,p,ov;
 assign {cy,z}=x+y;
 assign s=z[15];
 assign p=~^z;
 assign zr=~|z;
 assign ov=x[15]&y[15]&~z[15]|
~x[15]&~y[15]&z[15];
 endmodule
16 bit adder using behavioral(test
bench)
 module bit16_behavtest;
 reg [15:0]x,y;
 wire[15:0]z;
 wire cy,z,s,p,ov;
 bit16_behav dut(x,y,z,cy,zr,s,p,ov);
 initial
 begin
 $monitor($time,"x=%h,y=%h,z=%h,cy=%b,zrcy=%b,scy=
%b,pcy=%b,ovcy=%b",x,y,z,cy,zr,s,p,ov);
 #5 x=16h'8fff;y=16h'8000;
 #5 $finish;
 end
 endmodule
16 bit adder using structural
16 bit adder using structural
 module bit16_struc(x,y,z,cy,zr,s,p,ov);
 input [15:0]x,y;
 output[15:0]z;
 output cy,zr,s,p,ov;
 wire [3:1]c;
 assign s=z[15];
 assign p=~^z;
 assign zr=~|z;
 assign ov=x[15]&y[15]&~z[15]|~x[15]&~y[15]&z[15];
 ripple_4bit a0(z[3:0],c[1],x[3:0],y[3:0],1'b0);
 ripple_4bit a1(z[7:4],c[2],x[7:4],y[7:4],c[1]);
 ripple_4bit a2(z[11:8],c[3],x[11:8],y[11:8],c[2]);
 ripple_4bit a3(z[15:12],cy,x[15:12],y[15:12],c[3]);
 endmodule
Behavioral 2x1 mux*
 module mux21_1behv(in,sel,out)
 input [1:0]in;
 output out;
 input sel;
 assign out=in[sel];
 endmodule
structural 2x1 mux
structural 2x1 mux
 module mux2_1struct(in,sel,out)
 input [1:0]in;
 output out;
 input sel;
 wire t1,t2,t3;
 not g1(t1,sel);
 and g2(t2,in[0],t1);
 and g3(t3,in[1],sel);
 or g4(out,t2,t3);
 endmodule
Behavioral 4x1 mux
 module mux4_1beh(in,sel,out);
 input [3:0]in;
 output out;
 input [1:0]sel;
 assign out=in[sel];
 endmodule
structural 4x1 mux
structural 4x1 mux
 module mux4_1struc(in,sel,out);
 input [3:0]in;
 output out;
 input [1:0]sel;
 wire [1:0]t;
 mux2_1struct a0(in[1:0],sel[1],t[0]);
 mux2_1struct a1(in[3:2],sel[1],t[1]);
 mux2_1struct a2(t,sel[0],out);
 endmodule
Behavioral 16x1 mux
 module mux16_1beh(in,sel,out);
 input [15:0]in;
 output out;
 input [3:0]sel;
 assign out=in[sel];
 endmodule
Test 16x1 mux
 module mux16_1behtest;
 reg [15:0]in;
 wire out;
 reg [3:0]sel;
 mux16_1beh m(in,sel,out);
 initial
 begin
 $monitor($time,"in=%b,sel=%b,out=%b",in,sel,out);
 #5 in=16'h3f01;sel=4'h0;
 #5 sel=4'h1;
 #5 $finish;
 end
 endmodule
structural 16x1 mux
 module mux16_1struc(in,sel,out);
 input [15:0]in;
 output out;
 input [3:0]sel;
 wire [3:0]t;
 mux4_1struc b0(in[3:0],sel[1:0],t[0]);
 mux4_1struc b1(in[7:4],sel[1:0],t[1]);
 mux4_1struc b2(in[11:8],sel[1:0],t[2]);
 mux4_1struc b3(in[15:12],sel[1:0],t[3]);
 mux4_1struc b4(t,sel[3:2],out);
 endmodule
structural 16x1 mux
D flip flop

 module dff(d,en,q);
 input d,en;
 output q;
 assign q=en?d:q;
 endmodule
SR flip flop
 module srff(s,r,q,qb);
 input s,r;
 output q,qb;
 assign q=~(r&qb);
 assign qb=~(s&q);
 endmodule
SR flip flop