Design of springs

CHAPTER

1
Conversion 6. [NAT] [GATE-2014: 1M]
Consider the equation (123)5 = (x8)y with x and y as
1. [NAT] [GATE-2021: 1M]
unknown. The number of possible solutions is ____.
If x and y are two decimal digits and (0.1101)2 =
(0.8xy5)10, the decimal value of x + y is .
7. [MCQ] [GATE-2009: 1M]
(1217)8 is equivalent to
2. [MCQ] [GATE-2017: 1M]
(a) (1217)16 (b) (028F)16
The representation of the value of a 16-bit unsigned
(c) (2297)10 (d) (0B17)16
integer X in hexadecimal number system is BCA9.
The representation of the value of X in octal number 8. [MCQ] [GATE-2008: 1M]
system is Let r denote number system radix. The only value(s)
(a) 136251 (b) 736251 of r that satisfy the equation √121𝑟 = 11 is/are
r
(c) 571247 (d) 571244
(a) decimal 10 (b) decimal 11
(c) decimal 10 and 11 (d) any value > 2
3. [NAT] [GATE-2017: 1M]
Consider a quadratic equation x2 - 13x + 36 = 0 with Signed Binary Numbers
coefficients in a base b. The solutions of this equation 9. [MCQ] [GATE-2019: 1M]
in the same base b are x = 5 and x = 6. Then b =_____.
In 16-bit 2's complement representation, the decimal
number -28 is:
4. [NAT] [GATE-2015: 2M] (a) 1111 1111 0001 1100
Consider the euqation (43)x = (y3)8 where x and y are (b) 0000 0000 1110 0100
unknown. The number of possible solution is . (c) 1111 1111 1110 0100
(d) 1000 0000 1110 0100
10. [NAT] [GATE-2019: 1M]
5. [NAT] [GATE-2014: 1M]
Two numbers are chosen independently and
The base (or radix) of the number system such that the
uniformly at random from the set {1, 2, . . . . , 13}.
following equation holds is____________.
The probability (rounded off to 3 decimal places) that
312/20 = 13.1 their 4-bit (unsigned) binary representations have the
same most significant bit is ______.

9.1
GATE Wallah CS & IT Topic wise PYQs
 Digital Logic

11. [MCQ] [GATE-2019: 1M] 14. [NAT] [GATE-2016:1M]

Consider Z = X - Y, where X, Y and Z are all in sign- Consider an eight-bit ripple-carry adder for
magnitude form. X and Y are each represented in n
computing the sum of A and B, where A and B are
bits . To avoid overflow , the representation of Z
integers represented in 2’s complement form. If the
would require a minimum of :
decimal value of A is one, the decimal value of B that
(a) n bits (b) n – 1 bits
(c) n + 1 bits (d) n + 2 bits leads to the longest latency for the sum to stabilize is
_________.
12. [MCQ] [GATE-2018: 2M]
Consider the unsigned 8-bit fixed point binary number 15. [NAT] [GATE-2016:1M]
representation below, b7 b6 b5 b4 b3 ⋅ b2 b1 b0 where Let X be the number of distinct 16-bit integers in 2’s
the position of the binary point is between b3 and b2 . complement representation. Let Y be the number of
Assume b7 is the most significant bit. Some of the
distinct 16-bit integers in sign magnitude
decimal numbers listed below cannot be represented
exactly in the above representation: representation. Then X-Y is _________.

(i) 31.500 (ii) 0.875 (iii) 12.100 (iv) 3.001

Which one of the following statements is true? 16. [NAT] [GATE-2016: 1M]
(a) None of (i), (ii), (iii), (iv) can be exactly The 16-bit 2’s complement representation of an
represented integer is 1111 1111 1111 0101; its decimal
(b) Only (ii) cannot be exactly represented representation is___.
(c) Only (iii) and (iv) cannot be exactly
represented
17. [MCQ] [GATE-2013: 1M]
(d) Only (i) and (ii) cannot be exactly The smallest integer that can be represented by an 8-
represented bit number in 2’s complement form is
(a) – 256 (b) – 128
13. [MCQ] [GATE-2017:1M] (c) – 127 (d) 0
When two 8-bit numbers A . . . A and B . . .B in 2’s
7 0 7 0
complement representation (with A and B as the 18. [MCQ] [GATE-2010: 1M]
0 0
least significant bits) are added using a ripple-carry P is a 16-bit signed integer. The 2's complement
adder, the sum bits obtained are S . . . S and the carry
7 0 representation of P is (F87B)16. The 2's complement
bits are C . . . C .
7 0 representation of 8×P is
An overflow is said to have occurred if
(a) (C3D8)16 (b) (187B)16
(a) The carry bit C7 is 1
(c) (F878)16 (d) (987B)16
(b) All the carry bits (C7, … ,C0) are 1
(c) (𝐴 ∙ 𝐵 ∙ ̅̅̅ ̅̅̅̅ ̅̅̅̅
7 7 𝑆7 + 𝐴7 ∙ 𝐵7 ∙ 𝑆7 is 1.
)
(d) (𝐴 ∙ 𝐵 ∙ ̅̅̅ ̅̅̅̅ ̅̅̅̅
0 0 𝑆0 + 𝐴0 ∙ 𝐵0 ∙ 𝑆0 is 1.
)

❑❑❑
9.2
GATE Wallah CS & IT Topic wise PYQs
 Number System and binary Codes

1. (3 to 3) 2. (a) 3. (8 to 8) 4. (5 to 5)
5. (5 to 5) 6. (3 to 3) 7. (b) 8. (d)
9. (c) 10. (0.502 to 0.504) 11. (c) 12. (c)
13. (c) 14. (–1 to –1) 15. (1 to 1) 16. (– 11 to –11)
17. (b) 18. (a)

1. (3)
0.5 0.25 0.125 0.0625
(0.1 1 0 1)2 = ( )10
= 1 × 2–1 + 1× 2–2 + 1× 2–3 + 1× 2–4
3. (8)
= (0.5 + 0.25 +0+ 0.625) Given the base of quadratic equation is b.
= (0.8125)10 (1)b x2 – (13)b x + (36)b = (0)b
(0.8125)10= (0.8xy5)10 x2 – (b + 3)x + 3b + 6 = 0
x = 1 4 = 2, x+4=1+2=3 Let x = 5
25 – (b + 3)5 + 3b + 6 = 0
25 – 5b – 15 + 3b + 6 = 0
16 – 2b = 0
b=8
2. (a) Let x = 6
Given X = BCA9 in Hexadecimal format 36 – (b + 3)6 + 3b + 6 = 0
we know in Binary system B = 1011, C = 1100, 36 – 6b – 18 + 3b + 6 = 0
A = 1010, 9 = 1001 24 – 3b = 0
(B C A 9)16 → ( ? )2 →( ? )8 b=8
Therefore, convert hexadecimal number system first Hence correct answer is (8).
in binary then octal system.

(BCA 9)16 = (136251)8 4. (5)

Hence correct option is (a). (43)x = (y3)8 (43)x = (y3)8
4x + 3 = 8y + 3 x>4 y<8

9.3
GATE Wallah CS & IT Topic wise PYQ
 Digital Logic

4x = 8y  x 2 – 5x = 0
x = 2y
 ( x – 5) x =0
y<8
x=0 x=5
x>4 Therefore, x = 5

Hence, the base of the given number will be 5.

X Y Condition

2 1 (×)

4 2 (🗸)

6 3 (🗸) 6. (3)

4 Given equation
8 (🗸)
(123)5 = (x 8)y
10 5 (🗸) By Converting the above equation into decimal form

6 (1×52 + 2×51+ 3×50) = xy + 8

12 (🗸)
38 = xy + 8
14 7 (🗸) xy = 30
and (x < y) (y > 8)
Total 5 possible solution
The possible solutions are
x=1 y = 30 (✔)
x=2 y = 15 (✔)
x=3 y = 10 (✔)
5. (5)
x=5 y=6 (X)
Let x be the base of the given number From the above solution only 3 satisfies the given
condition.
( 312)x
= (13.1) x
( 20) x
The above number in Decimal will be given as

3 × x 2 + 1 × x1 + 2 × x 0
1 0
= 1× x1 + 3 × x0 + 1 × x–1 7. (b)
2×x +0×x

3x 2 + x + 2 1
= x +3+
2x x

3x 2 + x + 2 x 2 + 3x + 1 First write the given number in binary representation

 =
2x x Write each digit 3 bits

 3x 2 + x + 2 = 2x 2 + 6x + 2 (1217)8 = (001010001111)2

9.4
GATE Wallah CS & IT Topic wise PYQs
 Number System and binary Codes

Now, to represent the above number in hexadecimal Now taking 2’s complement of (0000 0000 0001
form, make the group of 4 bits. 1100)2=1111 1111 111 0100
(0010 1000 1111)2 = (028F)16 Hence
Hence, correct answer is option (b). –28 → 1111 1111 1110 0100
Therofre correct answer is option (C)
10. (0.502)
Decimal Unsigned representation
1 0001
8. (d)
2 0010
The given equation is 3 0011
4 0100
(121)r = (11)r
5 0101
Let r be any base 6 0110
4 0111
1 r 2 + 2  r1 + 1 r 0 = 1 r1 + 1 r 0 7 0111
8 1000
r 2 + 2r + 1 = r +1 9 1001
10 1010
( r + 1)
2
= r +1 11 1011
12 1100
 (r + 1) = r + 1
13 1101
Take negative sign From above table 7 number with MSB ‘O’
– (r + 1) = r + 1 6 number with MSB ‘1’
2r + 2 = 0 Two number are selected indepednely with same
MSB
r = –1 (radix cannot be negative)
Probability (P)=P (MSB = 0) + P(MSB = 1)
Take positive sign
7 7 6 6
r+1=r+1 Probability (P)=  + 
13 13 13 13
for all value which is greater than 2.
49 36
Probability (P)= + = 0.5029
Hence, correct answer is option (d). 169 169

9. (c) 11. (c)

To find 2’s complement of -28 first we convert +28 Overflow occurs when two same sign number are
in binary system and then take 2’s complement add/sub And result we get in different sign
(28)10 =(0000 0000 0001 1100)2 Example
3 bit sign number

9.5
GATE Wallah CS & IT Topic wise PYQ
 Digital Logic

(+3) + (1.2) = +5 To avoid overflow bit extension required

011
+
010
→ in signed it is –1
101
Extension of bit required to avoid overflow
Z=X–Y
↓ ↓
n-bit n-bit
To avoid overflow z should be (n + 1) bits

14. (–1)
Given:
A = 1 in decimal form
12. (c) binary form of A = 0000 0001
Given b7 b6 b5 b4 b3 ⋅ b2 b1 b0 For longest latency, we must have Cin = 1 at every
stage of ripple carry adder.
before . 5 bit that means we can represent at max Maximum delay will be given when we, take B = –1
3110 in decimal and (1111 1111) in binary
B=1 1 1 1 1 1 1 1  –1
after . 3 bit that means total 8 comibanations are
A=0 0 0 0 0 0 0 1 → +1
Binary Decimal Carry out = 1 0 0 0 0 0 0 0 0
000 0.000
001 0.125
010 0.250
15. (1)
011 0.375
If x is in 2’s then range of x will be
100 0.500 –2n–1 to 2n–1 –1
101 0.625 Here x is 16 bits number, n = 16
–216–1 to 216–1 –1
110 0.750
x = 65536
111 0.875 If y is in sign magnitude representation, then range
of y will be
From above analysis we can't represent (0.100)10
– (2n–1–1) to + (2n–1 –1) n = 16
and (0.001)10 16–1 16–1
– (2 –1) to + (2 –1)
From above analysis only (iii) and (iv) cannot be y = 65535
exactly same represented. Hence, x – y = 1
13. (c)
Overflow:
When two same sign number are added and result we
will get in different sign.

9.6
GATE Wallah CS & IT Topic wise PYQs
 Number System and binary Codes

16. (–11)
Given 16-bit number is 1111 1111 1111 0101 18. (a)

Here MSB bit is 1 that means the given number is Method 1:

The given number is
negative signed number
P = (F87B)16
P = 1111100001111011 = (–1925)
2’s complement of the above number will be given
as
= 0000011110000101
Its decimal representation will be
 1 × 210 + 1 × 29 + 1×28 + 1 × 2 + 4 + 2
7

2's complement of given number is 0000 0000 0000

 1024 + 512 + 256 + 128 + 4+1 = 1925
1011, which is equivalent to + 11 but MSB here is 1
Now,
hence number is negative i.e - 11 and correct answer
is -11. 8 × P = 8 × (–1925) = –15400
Its binary representation will be 0011110000101000
Now, 2’s complement of the above number will be
given as
1100001111011000
17. (b) 8P →(C3D8)16
For 2’s Complement form Hence, correct answer is option (a)
The range will be given by Method 2:
– (2n–1) to + (2n–1 –1) P = (F87B)16
For n = 8 (Given 8 bit number) = 1111100001111011
The minimum will be
By multiplying 21 , number will be shifted to left by
 – (28–1) one position, and by multiplying 23 , number will be
 – (27) shifted by 3 position to the left.
 –128  11 00 00 1111011000
The maximum number will be given as
8P  (C3D8)16
(2n–1) = 127
Hence, correct answer is option (a)
Hence, correct answer is option (b).

❑❑❑

9.7
GATE Wallah CS & IT Topic wise PYQ
 Design of springs

CHAPTER

2
Boolean Algebra 4. [MCQ] [GATE-2015: 1M]

1. [MCQ] [GATE-2022: 1M] The number of min-terms after minimizing the

following Boolean expression is ______ .
The dual of a Boolean function F(x1, x2, ..., x, +, ⋅, ‘ ),
written as FD, is the same expression as that of F with [D' + AB' + A'C + AC'D + A'C'D] '
+ and ⋅ swapped. F is said to be self-dual if F = FD.
(a) 1 (b) 2
The number of self-dual functions with n Boolean
variables is (c) 3 (d) 4
(a) 2n (b) 2n-1 5. [MCQ] [GATE-2015: 2M]
𝑛 𝑛−1
(c) 22 (d) 22 Given the function F = P’ + QR, wehre F is a function
in three Boolean variables P,Q and R and P’ = !P,
2. [MCQ] [GATE-2017: 1M] consider the following statements.
If w, x, y, z are Boolean variables, then which one of (S1) F = (4, 5, 6)
the following is INCORRECT?
(a) wx + w(x + y) + x(x + y) = x + wy (S2) F = (0,1,2,3,7)
̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(b) wx ̅(y + z̅)+w ̅x = w ̅ + x + y̅z (S3) F = (4, 5, 6)
(c) wx̅ y + xz̅ + w
( ( ) )
̅ x̅ y = xy̅
(S4) F = (0,1,2,3,7)
(d) (w + y)(wxy + wyz) = wxy + wyz
Which of the following is true?

3. [MCQ] [GATE-2015: 1M] (a) (S1) – False, (S2) – True, (S3) – True, (S4) -False
(b) (S1) – True, (S2) – False, (S3) – False, (S4) -True
The binary operator ≠ is defined by the following
truth table (c) (S1) – False, (S2) – False, (S3) – True, (S4) -True
(d) (S1) – True, (S2) – True, (S3) – False, (S4) -False
P Q p≠q
6. [MCQ] [GATE-2012: 1M]
0 0 0
The truth table
0 1 1
1 0 1 X Y F(X,Y)
0 0 0
1 1 0
0 1 0
Which one of the following is true about the binary 1 0 1
operator ≠? 1 1 1
(a) Both commutative and associative represents the Boolean function
(b) Commutative but not associative
(c) Not commutative but associative (a) x (b) x + y
(d) Neither commutative nor associative (c) x  y (d) y

9.8
GATE Wallah CS & IT Topic wise PYQs
 Boolean Algebra, Logic Gates and K-Maps

7. [MCQ] [GATE-2012: 1M] 12. [MCQ] [GATE-2022: 1M]

The amount of ROM needed to implement a 4 bit Consider the Boolean operator # with the following
multiplier is properties:

(a) 64 bits (b) 128 bits x # 0 = x, x #1 = 𝑥̅ , x # x = 0 and x # 𝑥̅ = 1

(c) 1 Kbits (d) 2 Kbits Then x # y is equivalent to

8. [MCQ] [GATE-2011: 1M] (a) x𝑦̅ + 𝑥̅ y (b) x𝑦̅ + 𝑥̅ 𝑦̅

The simplified SOP (sum of product) form of the (c) 𝑥̅ y + xy (d) xy + 𝑥̅ 𝑦̅
boolean expression
13. [MCQ] [GATE-2020: 2M]
(𝑃 + 𝑄̅ + 𝑅̅ ) ∙ (𝑃 + 𝑄̅ + 𝑅) ∙ (𝑃 + 𝑄 + 𝑅̅)
Consider the Boolean function z(a,b,c).
(a) ( P.Q + R ) (b) ( P + Q'.R ')
Which one of the following minterm lists represents
(c) ( P '.Q + R ) (d) ( P. Q + R ) the circuit given above?
9. [MCQ] [GATE-2011: 1M]
̅+
The minterm expansion of f(P, Q, R) = PQ + QR
̅ is
PR
(a) m2 + m4 + m6 + m7 (b) m0 + m1 + m3 + m5
(c) m0 + m1 + m6 + m7 (d) m2 + m3 + m4 + m5
(a) Z = Σ (0, 1, 3, 7)
(b) Z = Σ (2, 4, 5, 6, 7)
10. [MCQ] [GATE-2008: 1M]
(c) Z = Σ (1, 4, 5, 6, 7)
If P, Q, R are Boolean variables, then (P + Q) (P.Q +
P.R) (P.R + Q) Simplifies to (d) Z = Σ (2, 3, 5)
(a) P. Q
(b) P. R 14. [MCQ] [GATE-2019: 1M]
(c) P. Q + R
Which one of the following is NOT a valid identity?
(d) P.R + Q (a) (x + y) ⊕ z = x ⊕ (y + z)
Logic Gates (b) (x ⊕ y) ⊕ z = x ⊕ (y ⊕ z)
(c) x ⊕ y = x + y, if xy = 0
11. [MCQ] [GATE-2022: 1M]
(d) x ⊕ y = (xy + x'y')'
Let, x ⊕ x ⊕ x ⊕ x = 0 where x , x , x , x are
1 2 3 4 1 2 3 4
Boolean variables, and ⊕ is the XOR operator.
Which one of the following must always be TRUE?
15. [MCQ] [GATE-2019: 2M]
(a) x x x x = 0 What is the minimum number of 2-input NOR gates
1 2 3 4
required to implement a 4-variable function expressed
(b) x x +x = 0
1 3 2 in sum-of-minterms form as f = Σ(0, 2, 5, 7, 8, 10, 13,
(c) ̅̅̅
𝑥1 ⨁ ̅̅̅
𝑥3 = ̅̅̅
𝑥2 ⨁ ̅̅̅
𝑥4 15)? Assume that all the inputs and their complements
(d) x +x + x + x = 0
1 2 3 4 are available._______

9.9
GATE Wallah CS & IT Topic wise PYQs
 Digital Logic

16. [MCQ] [GATE-2019: 2M] 19. [MCQ] [GATE-2013: 1M]

Consider three 4-variable functions f1, f2 and f3, Which one of the following expressions does NOT
represent exclusive NOR of x and y?
which are expressed in sum-of-minterms as
(a) xy + x'y' (b) x  y'
f1 = Σ(0, 2, 5, 8, 14), f2 = Σ(2, 3, 6, 8, 14, 15), f3 = (c) x'  y (d) x'  y'
Σ(2, 7, 11, 14)
20. [MCQ] [GATE-2011: 1M]
For the following circuit with one AND gate and one
XOR gate, the output function f can be expressed as: Which one of the following circuits is NOT equivalent
to a 2-input X-NOR (exclusive NOR) gate?

(a)

(b)

(a) Σ (2, 14) (c)

(b) Σ (7, 8, 11)
(c) Σ (2, 7, 8, 11, 14) (d)
(d) Σ (0, 2, 3, 5, 6, 7, 8, 11, 14, 15)
17. [MCQ] [GATE-2018: 1M]
21. [MCQ] [GATE-2010: 1M]
Let ⊕ and ⊙ denote the Exclusive OR and Exclusive What is the Boolean expression for the output f of the
NOR operations, respectively. Which one of the combinational logic circuit of NOR gates given
following is NOT CORRECT? below?
(a) P  Q = P
P
Q Q

(b) P  Q = P Q P
Q f
(c) P  Q = P  Q
P

( ) ( )
Q
(d) P  P  Q = P P Q
P
18. [MCQ] [GATE-2014: 1M] Q

(a) Q + R (b) P + Q
Let ⨁denote the Exclusive OR (XOR) operation. Let
‘1’ and ‘0’ denote the binary constants. Consider the (c) P + R (d) P + Q + R
following Boolean expression for F over two
variables P and Q:
22. [MCQ] [GATE-2009: 1M]
F(P, Q) = ((1⨁𝑃)⨁(𝑃⨁𝑄))⨁((𝑃⨁𝑄)⨁(𝑄⨁0))
What is the minimum number of gates required to
The equivalent expression for F is
implement the Boolean function (AB + C) if we have
(a) P + Q (b) (P + Q) to use only 2-input NOR gates?
(c) P ⨁ Q (d) (P ⨁ Q) Q) ’ (a) 2 (b) 3
(c) 4 (d) 5

9.10
GATE Wallah CS & IT Topic wise PYQs
 Boolean Algebra, Logic Gates and K-Maps

23. [MCQ] [GATE-2008: 1M] 27. [NAT] [GATE-2017: 1M]

A set of Boolean connectives is functionally complete Consider the Karnaugh map given below, where X
represents “don’t care” and blank represents 0.
if all Boolean functions can be synthesized using
those. Which of the following sets of connectives is
NOT functionally complete?

(a) EX-NOR (b) implication, negation

(c) OR, negation (d) NAND

24. [MCQ] [GATE-2008: 1M]

Given f1,f3 and f in canonical sum of products from
(in decimal) for the circuit.
Assume for all inputs(a, b, c, d) , the respective
complements (𝑎̅, 𝑏̅, 𝑐̅, 𝑑̅ ) are also available. The
above logic is implemented using 2-input NOR gates
only. The minimum number of gates required is
_________.

28. [MCQ] [GATE-2017: 1M]

F1 = m (4,5,6,7,8)
Given f(w, x, y, z) = Σm(0, 1, 2, 3, 7, 8, 10) + Σd(5, 6,
F3 = m (1, 6, 15) 11, 15), where d represents the don’t-care condition in
F = m (1, 6, 8, 15) Karnaugh maps. Which of the following is a
Then f2 is minimum product-of-sums (POS) form of f(w, x, y, z)?
(a) m (4, 6) (b) m (4, 8) (a) 𝑓 = (𝑤
̅ + 𝑧̅)(𝑥̅ + 𝑧)
(c) m (6, 8) (d) m (4, 6, 8) (b) 𝑓 = (𝑤
̅ + 𝑧)(𝑥 + 𝑧)
K-Maps (c) 𝑓 = (𝑤 + 𝑧)(𝑥̅ + 𝑧)
25. [NAT] [GATE-2022: 1M] (d) 𝑓 = (𝑤 + 𝑧̅)(𝑥̅ + 𝑧)

The total number of prime implicants of the function 29. [MCQ] [GATE-2014: 1M]
f(w,x,y,z) = Σ(0, 2, 4, 5, 6, 10) is ______. Consider the following Boolean expression for F:
26. [NAT] [GATE-2018: 2M] F(P, Q, R, S) = PQ + P'QR + P'QR'S
Consider the minterm list form of a Boolean function The minimal sum-of-products form of F is
F given below.
(a) PQ +QR +QSz
F(P, Q, R, S) = Σm(0, 2, 5, 7, 9, 11) + d(3, 8, 10, 12,
(b) P + Q + R + S
14)
(c) ̅ ̅+R
P+Q ̅ + S̅
Here, m denotes a minterm and d denotes a don’t care
term. The number of essential prime implicants of the (d) ̅
PR + ̅
PR̅S + P
function F is _______ .

9.11
GATE Wallah CS & IT Topic wise PYQs
 Digital Logic

30. [MCQ] [GATE-2014: 1M] 32. [MCQ] [GATE-2008: 1M]

Consider the following minterm expression for F: In the Karnaugh map shown below, X denotes a don’t
care term. What is the minimal form of the function
F (P,Q,R,S) = ∑ 0, 2, 5, 7, 8,10,13,15
represented by the Karnaugh map?
The minterms 2, 7, 8 and 13 are 'do not care’ terms. ab
cd 00 01 11 10
The minimal sum-of-products form for F is
00 1 1 1
(a) QS + QS (b) QS + QS
01 ×
(c) QRS + QRS + QRS + QRS
11 ×
(d) PQS + PQS + PQS + PQS
10 1 1 ×

(a) b. d + a. d
31. [MCQ] [GATE-2012: 1M] (b) a. b + b. d + a.b.d
What is the minimal form of the karnaugh map shown (c) b. d + a.b. d
below? Assume that X denotes a don't care term (d) a. b + b. d + a. d
ab
cd 00 01 11 10
33. [MCQ] [GATE-2008: 1M]
00 1 × × 1 Consider the following Boolean function of four
01 × 1 variables f(A, B, C, D) = Σ(2, 3, 6, 7, 8, 9, 10, 11, 12,
11 13) The function is

10 1 × (a) independent of one variable

(b) independent of two variables
(a) bd (b) bd + bc
(c) independent of three variable
(c) bd + abcd (d) bd + bc + cd
(d) dependent on all the variables

❑❑❑

9.12
GATE Wallah CS & IT Topic wise PYQs
 Boolean Algebra, Logic Gates and K-Maps

1. (d) 2. (c) 3. (b) 4. (a)

5. (a) 6. (a) 7. (d) 8. (b)
9. (a) 10. (a) 11. (c) 12. (a)
13. (c) 14. (a) 15. (3) 16. (b)
17. (d) 18. (d) 19. (d) 20. (d)
21. (a) 22. (b) 23. (a) 24. (c)
25. (3) 26. (3) 27. (1) 28. (a)
29. (a) 30. (b) 31. (b) 32. (a)
33. (a)

1. (d) FD= AB + BC + AC
For n = 1, Total number of functions = 4 Hence, correct answer is option (d)

Total number of self-dual functions = 2

For n = 2, Total number of functions = 16
Total number self-dual functions = 4
Now, if we have ‘n’ variable with us 2. (c)
n
(a) wx + w (x +y) + x(x +y) = x +wy
Then total number of function = 22 wx + wx +wy + x + xy
Among then number of self-dual functions x [w +w + 1+ y] + wy
= x + wy
n–1
= 22 Therefore, option a is correct
Self -Dual: (b) ( )
wx y + z + wx = w + x + yz
F = FD wx + y+z + wx
F = AB w + x + yz + wx
FD = A+B
( )
w + x 1 + w + yz = w + x + yz
A ⎯⎯⎯
→A Dual
Therefore, option b is correct
A ⎯⎯⎯
→A Dual
(c) ( wx ( y + xz ) + wx ) y = xy
Ex-
wx y + w x x z + w x y
F = AB + BC + AC
FD = (A + B) (B + C) (A + C)  wxy + wx y 
 

9.13
GATE Wallah CS & IT Topic wise PYQs
 Digital Logic

(
xy w + w )  CD  A  A + AC + AB + BC 

xy  CD  AC+AB + BC 
Hence correct answer is option (c)
= AC  CD + ABCD + BCCD
(d) (w + y) (wxy + wyz) = wxy +wyz  ABCD
wxy +wyz + wxy + wyz
Hence, correct answer is option (a).
wxy + wyz
Therefore, option d is correct.

5. (a)
Standard mininmal from
3. (b)
F = P + QR
We can see that the given truth table is the output of
X ᠆ OR gate and we know that X-OR logic follows ( )( ) (
F = P Q + Q R + Q + P + P QR )
both commutative and associative operation. = PQR + PQR+PQR + PQR+PQR+PQR+PQR
A  B = B  A → follow commutative law
= m(0,1,2,3,7)
(A  B)  C = A  (B  C) Follow associative = M (4,5,6)
law.
Hence, correct answer is option (a).

6. (a)
4. (a) The equation of the given truth table will be given as
The given Boolean expression is F ( x,y ) = xy + xy
= D + AB + AC + ACD +ACD (
=x y+y =x )
= D + AB + AC + CD A+A ( ) Hence, correct answer is option (a)

= D + AB + AC + CD

= D + CD + AB + AC

= ( C+D )( D+D ) + AB + AC 7. (d)

(
 C+D + AB + AC ) ( ) Let us see the 4-bit number multiplication.
 C + D  AB  AC

 CD  A + B   A + C 

9.8
GATE Wallah CS & IT Topic wise PYQs
 Boolean Algebra, Logic Gates and K-Maps

Input = 24 × 24 output = 8
The amount of ROM needed to implement a 4 bit
( ) ( ) (
F ( P,Q,R ) = PQ R + R + P + P QR + P Q + Q R )
multiplier is = PQR + PQR + PQR + PQR + PQR + PQR
ROM = 2 4 × 24 × 8
= m6 + m7 + m2 + m6 + m4 + m6
= 28 ×23
= 211 = m2 + m4 + m6 + m7
= 2 × 210
Hence, correct answer is option (a).
= 2k bits
Hence, correct answer is option (d).

10. (a)
The given expression is
8. (b)
(P + Q) (P.Q + P.R) (P.R + Q)
The given expression is
( )(
 PQ + PR + PQ + PQR  PR + Q )
(𝑃 + 𝑄̅ + 𝑅̅ ) ∙ (𝑃 + 𝑄̅ + 𝑅) ∙ (𝑃 + 𝑄 + 𝑅̅)  ( PQ + PR )  ( PR + Q )

= P ( Q + R )  ( PR + Q )
Let P + Q = x

( ) (
⇒ x + R (x + R) P + Q + R ) = ( Q + R )( PPR + PQ )

(By distribution Theorem x + R̅ . R = (x + R̅) (x + R) ) = ( Q + R )( PQ )

⇒ x. (P + Q + R̅) = PQ + PQR
= PQ (1 + R )
( )(
⇒ P+Q  P+Q+R ) = PQ
 P + PQ + PR + PQ + Q  Q + QR Hence, correct answer is option (a).

= P 1 + Q +R + Q + Q R

= P + Q̅ R̅
Hence, correct answer is option (b).
11. (c)
We will put X1 = 1, X2 = 1, X3 = 1, X4 = 1
1111=0
By taking the above values ,we will see all the
options one-by-one.
9. (a) → X 1. X 2. X 3. X 4 = 1.1.1.1 = 0 (wrong)
→ X 1 X 3+ X 2 = 1.1 + 1 = 0 (wrong)
The given expression is
→ X  X 3 = X2  X4 = 0  0 = 0  0 = 0
F ( P,Q,R ) = PQ + QR + PR
(correct)
The Standard canonical form of the above → X 1+ X 2+ X 3+X4 = 0 (wrong)
expression will be given as:

9.9
GATE Wallah CS & IT Topic wise PYQs
 Digital Logic

Alternate Method: z = a(b̅ + b) (c̅ + c) + (a̅ + a) b̅ c

If A  B = 0 z= ab̅c̅ + ab̅c + abc̅ + abc + a̅b̅c+ ab̅ c

Then A  0 = B … (i) z=Σm (1,4, 5, 6, 7 )

Hence correct answer is option (c).
Given, x1 ⊕ x2 ⊕ x3 ⊕ x4 = 0

A = x1  x2, B = x3  x4
Substitute values of A, B in equation (i)
x1  x2  0 = x3  x4
x1  x2 = x 3  x4 14. (a)
Option (a)
We know that A  B = A  B
(x + y) ⊕ z = x ⊕ (y + z)
x1  x 2 = x 3  x 4
̅̅̅̅̅̅̅
(x + y) ⊕ z= (x + y) z̅ + (𝑥 + 𝑦) z
x1  x 2 = x3  x 4 (x + y) ⊕ z= xz̅ + y z̅ + x̅ y̅ z
Hence, correct answer is option (c) ̅̅̅̅̅̅̅
x ⊕ (y+z)=x(𝑦 + 𝑧) +x̅ (y + z)
x ⊕ (y+z)=x y̅ z̅ + x̅ y + x̅ z
(x + y) ⊕ z ≠ x⊕(y + z)
Option (b)

12. (a) (x ⊕ y) ⊕ z = x ⊕ (y ⊕ z)
X-OR gate follows associative law
Given
x # 0 = x, x #1 = 𝑥̅ , Option (c)

x#x=0, x # 𝑥̅ = 1 x ⊕ y = x + y, if x.y = 0
We can see from the given condition that the logic x ⊕ y = x̅y + xy̅
operator # resembles the logic of EX-OR gate. = (x + y) (x̅ + y̅)
Therefore,
= (x + y) = 1 = x+y
x # y = xy +xy
𝑥𝑦 = 1
̅̅̅
Hence correct answer is option (a)
x̅ + y̅ = 1
Option (d)
x ⊕ y = (xy + x̅ y̅)
x ⊕ y = ̅̅̅̅̅̅̅̅
𝑥⊙y
13. (c)
̅̅̅̅̅̅̅̅̅̅̅̅
x ⊕ y =xy + x̅ y̅
Hence option (a) is correct answer.

z = a + b̅ c
standard canonical form

9.10
GATE Wallah CS & IT Topic wise PYQs
 Boolean Algebra, Logic Gates and K-Maps

15. (3) P = f1  f2
F = Σm (0, 2, 5, 7, 8, 10, 13, 15) P = (0, 2, 5, 8, 14)  (2, 3, 6, 8, 14, 15)
P = (2, 8, 14)

f = P  f3

f = P f3 + P f3

P f3 = (2, 8, 14)  (0, 1, 3, 5, 6, 8, 9, 10, 12, 13, 15)

Simplified expression from above K-Map P f3 = (8)

In SOP P f3 = (0, 1, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 15)  (2, 7,

F= B̅D̅ + BD 11, 14)
In POS P f3 = (7, 11)
F= (B̅ + D) (B + D̅)
f = (8)  (7, 11)
f = (7, 8, 11)
f =  (7, 8, 11)

17. (d)
From above logic circuit minimum number NOR gate
required is 3. Option (b)

f = P̅ ⊕ Q

16. (b) Let P̅ = Z

Given f = Z ⊕ Q= Z̅Q + Z Q̅

f1 = (0, 2, 5, 8, 14) f=̅

P̅ Q + P̅Q̅ = PQ + P̅Q̅ = P ⊙ Q

f2 = (2, 3, 6, 8, 14, 15)

f3 =  (2, 7, 11, 14)

Hence option (b) is correct

Option (c)

9.11
GATE Wallah CS & IT Topic wise PYQs
 Digital Logic

P̅ ⊕ Q̅ = P̅ Q̅ + P̅ Q̅ = ( ( x '+ y )( x + y') )
= PQ̅ + P̅ Q
= x'y' + xy
=P⊕Q
→ xy + x'y' = x y [Exclusive OR]
Hence option (c) is correct
→ x  y' = x y [Exclusive OR]
Option (d)
→ x'  y = x y [Exclusive OR]
(P ⊕ P̅ ) ⊕Q = (P ⊙ P̅ ) ⊙Q̅
→ x'  y' = x  y [Exclusive NOR]
1 ⊕ Q = Q̅ ≠ O ⊙ Q̅ = Q
Hence, correct answer is option (d).
Hence option (d) is incorrect.

20. (d)
18. (d)
Let us see the output of all the given options we get
Let P  Q = Z
F = (1  P )  ( Z)  ( Z)  ( Q  0) (a)

=  P  P  Q    P  Q  Q

= 1  Q   P  0 (b)

= QP
(c)
= PQ

P  1 = P

Q  0 = Q
Note: 
P  Q = P Q = PQ
Z  Z = O

(d)
Hence, correct answer is option (d).

Hence, correct answer is option (d).

19. (d)
We know that Exclusive NOR of x and y

( )
= xy

= ( x  y ) = ( xy' + x'y ) '

9.12
GATE Wallah CS & IT Topic wise PYQs
 Boolean Algebra, Logic Gates and K-Maps

21. (a) Hence, three NOR gates will be required to

Let us see the output of the given logic circuit at implement f as shown below

each stage, we get

Hence, correct answer is option (b).

The output of the above logic circuit will be given

by

( )(
f = PQ + QR PR + QR ) 23. (a)
f = PQR + PQR + PQR + QR We now, that
f = PQR + QR
NAND/NOR is functionally complete.
( )
f = QR P+1

f = Q +R

Hence, correct answer is option (a).

22. (b) And from the above options only EX-NOR is not
The given expression is
functionally complete
f = (AB + C)
Hence, correct answer is option (a).
By using distribution theorem, we can write above
expression as
f = (A + C)  (B + C)
Note: Whenever in the problem, NOR gates are
asked, write the function in POS.
Now, the above expression is in POS form.

9.13
GATE Wallah CS & IT Topic wise PYQs
 Digital Logic

24. (c)

From above K-Map number of Essential prime

25. (3) implicats is 3.
The given function is
f(w,x,y,z) = Σ(0, 2, 4, 5, 6, 10)
The k-map of the above function will be given as
below
27. (1)
The given k-map is shown below

here only one quad group is possible then

From the above k-map
therefore,representation of given k map is
F = WZ + WXY + XYZ
F= a c= a+c=a c
 Total prime implicants = 3

Hence only one 2-input NOR gate required.

26. (3)
K-Map of given boolean function F

9.14
GATE Wallah CS & IT Topic wise PYQs
 Boolean Algebra, Logic Gates and K-Maps

28. (a) Hence, correct answer is option (a).

f(w, x, y, z) = Σm(0, 1, 2, 3, 7, 8, 10) + Σd(5, 6, 11, 15)

30. (b)
The given function is
F (P,Q,R,S) = ∑ 0, 2, 5, 7, 8,10,13,15
The k-map of the above functions is given below

from above K-Map 2 quad is possible

Therefore f(w,x,y,z) = ( x + z) ( w + z )
Hence option answer is option (a).

From the above k-map

F = Q S + QS
29. (a)
The given function is Hence, correct answer is option (b).

F (P, Q, R, S) = PQ + P Q R S
Its standard canonical form will be
F (P, Q, R, S) = PQ (R̅ + R) (S̅ + S) + P̅QR (S̅ + S) + P̅ Q
R̅ S
( )( )
F(P, Q, R, S) = PQ R + R S + S + R Q R S + S ( ) 31. (b) The given k-map is as shown below
+P Q R S
= PQR S + PQ RS + PQR S + PQRS + PQRS +
PQRS + PQRS
m = (12, 13, 14, 15, 6, 7, 5)
Now, the k-map of the above function will be given
as below

From the given k-map ,function f will be given as

f = b̅ c̅ + b̅ d̅
Hence correct answer is option (b).

= PQ + QS + QR 32. (a)

9.15
GATE Wallah CS & IT Topic wise PYQs
 Digital Logic

Given truth table is

From the above k-map the function f will be given as

f = a d + bd
Hence, correct answer is option (a).

33. (a)
f = AC + AC + AB
The given expression is
f = AC + AC + B C
f (A, B, C, D) = m(2, 3, 6, 7, 8, 9, 10, 11, 12 13)
We can see from the above expression that f is
k-map of the above expression will be given as
independent of D.
Hence, correct answer is option (a).

❑❑❑

9.16
GATE Wallah CS & IT Topic wise PYQs
 Design of springs

CHAPTER

3
BCD Adder and Subtractor Which one of the following set of values of (X0, X1,
X2, X3, X4, X5, X6, X7) will realise the Boolean
1. [NAT] [GATE-2016: 1M]
function A +A .C +A.B .C ?
Consider an eight-bit ripple-carry adder for
(a) (1, 1, 0, 0, 1, 1, 1, 0)
computing the sum of A and B where A and B are
integers represented in 2’s complement from. If the (b) (1, 1, 0, 0, 1, 1, 0, 1)
decimal value of A is one, the decimal value of B that (c) (1, 1, 0, 1, 1, 1, 0, 0)
leads to the longest latency for the sum to stabilize (d) (0, 0, 1, 1, 0, 1, 1, 1)
is .

Multiplexer
3. [MCQ] [GATE-2021: 1M]
2. [MCQ] [GATE-2023: 2M]
Which one of the folloiwng circuits implements the
A Boolean digital circuit is composed using two 4-
input multiplexers (M1 and M2) and one 2-input Boolean function given below?
multiplexer (M3) as shown in the figure. X0-X7 are f(x,y,z,) = m0+ m1+ m3+ m4 + m5+ m6 where mt is the
the inputs of the multiplexers M1 and M2 and could
ith minterm.
be connected to either 0 or 1. The select lines of the
multiplexers are connected to Boolean variables A, B 1 0
and C as shown. 1 1 4×1
MUX f
(a) x 2
x' 3 S1 S0

y z

x 0
1 1 4×1
MUX f
(b) x' 2
1 3 S1 S0

y z

9.17
GATE Wallah CS & IT Topic wise PYQs
 Digital Logic

1 0 6. [MCQ] [GATE-2016: 1M]

1 1 4×1 Consider the two cascaded 2 to 1 multiplexers as
(c) MUX f shown in the figure.
x' 2
–
x 3 S1
R
S0
0 0 2–to–1 0 2–to–1 X
y z MUX MUX
R 1 1
S S
x' 0
1 1 4×1 P Q
(d) MUX f
x 2 The minimal sum of products form of the output X is
1 3 S1 S0 (a) 𝑃̅𝑄̅ + 𝑃𝑄𝑅 (b) 𝑃̅Q+QR
(c) PQ+ 𝑃̅𝑄̅ R (d) 𝑄̅𝑅̅ +PQR
y z
7. [MCQ] [GATE-2014: 1M]
4. [NAT] [GATE-2020: 1M]
Consider the following combinational function block
A multiplexer is placed between a group of 32
involving four Boolean variables x, y, a, b where x, a,
registers and an accumulator to regulate data
b are inputs and y is the output.
movement such that at any given point in time the
f (x, y, a, b)
content of only one register will move to the
{
accumulator. The number of select lines needed for
the multiplexer is _____. if (x is 1) y = a;
else y = b;
5. [MCQ] [GATE-2014: 2M]
}.
Consider the 4-to-1 multiplexer with with two select
Which one of the following digital logic blocks is the
S1 and S0 given below. most suitable for implementing this function?
(a) Full adder (b) Priority encoder
(c) Multiplexer (d) Flip-flop
8. [MCQ] [GATE-2010: 1M]
The Boolean expression of the output f of the
multiplexer shown below is

The minimal sum of products from the Boolean

expression for the output F of the multiplexer is-

(a) PQ + QR + PQR

(b) PQ + PQR + PQR + PQR

(c) PQR + PQR + QR + PQR

(d) PQR (a) P  Q  R (b) P  Q  R

(c) P + Q + R (d) P + Q + R

9.18
GATE Wallah CS & IT Topic wise PYQs
 Combinational Logic Circuits

Decoder/De-MUX Encoder and Priority Encoder

9. [NAT] [GATE-2020: 1M] 11. [MCQ] [GATE-2013: 1M]
If there are m input lines and n output lines for a In the following truth table, V = 1 if and only if the
decoder that is used to uniquely address a byte input is valid. What function does the truth table
addressable 1 KB RAM, then the minimum value of represent?
m + n is ____.
Inputs Outputs
10. [MCQ] [GATE-2008: 1M]
D0 D1 D2 D3 X0 X1 V
What Boolean function does the circuit below
0 0 0 0 x x 0
realize?
1 0 0 0 0 0 1
X 1 0 0 0 1 1
X x 1 0 1 0 1
X x x 1 1 1 1

(a) xz + x z (b) x z + x z What function does the truth table represent?

(c) x y + yz (d) xy + y z (a) Priority encoder (b) Decoder

(c) Multiplexer (d) Demultiplexer

❑❑❑

9.19
GATE Wallah CS & IT Topic wise PYQs
 Digital Logic

1. (–1) 2. (c) 3. (a) 4. (5)

5. (a) 6. (d) 7. (c) 8. (b)
9. (1034) 10. (b) 11. (a)

1. (–1)
B = 1 1 1 1 1 1 1 1  –1

2. (c)

Given function f (ABC) = A + AC + AB C

• First, we minimize the given function
f (ABC) =  (X0 X1 X2 X3 X4 X5 X6 X7) = (11011100)
( )( ) ( )
A B + B C + C + A B + B C + AB C Hence correct answer is option (c).
f (ABC) =
ABC + AB C+ ABC + ABC + ABC + ABC + ABC

f (ABC) = ABC + AB C+ ABC + ABC + ABC + ABC

f (ABC) = m (0, 1, 2, 3, 5) 3. (a)
Now implementing on 2 × 1 mux. ( ) ( )
F = X + X YZ + X + X YZ + XYZ + XYZ

= XYZ + XYZ + XYZ + XYZ + XYZ + XYZ

=  m ( 0,1,3,4,5,6)

9.20
GATE Wallah CS & IT Topic wise PYQs
 Combinational Logic Circuits

4. (5) If S0 is enabled and x, y are inputs then output

f= S̅0 x + S0 y
Given:
Here in given problem output of MUX-1 is input to
Number of registers = 32
MUX -2
Mux ⇒ 32 × 1 output MUX -1
f1 = P̅.0 + P.R = P R
Inputs = 32
MUX -2 output
Number of select line = log2(number of inputs) X = Q̅. R̅ + Q. f1
Number of select line =log232 = 5 X = Q̅. R̅ + Q.P.R
Its minimal sum of product form output
X= Q̅.R̅ + PQR
Hence, correct answer is option (d).

5. (a)

F = PQ + PQR + PQR
Standard cononcial from 7. (c)
( )
F= PQ R + R + PQR + PQR Then given circuit will be as follows

= PQR + PQR+PQR + PQR =  m ( 2,3,5,6 )

From the given condition if

x =1 y=a
PQR + PQ + QR Otherwise, y = b
The truth table of the above circuit will be given as
x a b y
0 0 0 0
0 0 1 1
6. (d)
0 1 0 0
General 2:1 Mux expression
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

9.21
GATE Wallah CS & IT Topic wise PYQs
 Digital Logic

y (x, a, b) = m(1, 3, 6, 7)

The k-map of the above function will be

f = PQR + PQR + PQR + PQR

f =PQR
Hence, correct answer is option (b).
y=xa+ x b

9. (1034)

Hence, correct answer is option (c).

1 kB RAM=1024 = 210

m = 10
8. (b)
n = 210 = 1024
Given multiplexer diagram redrawn as
m + n = 10 + 1024= 1034

10. (b)

The output of the given multiplexer will be given as

f = PQR + PQR + PQR + PQR

f = m1 + m2 + m4 + m7
We can see that the given circuit is 3 to 8
f =  m (1, 2, 4,7 )
decoder and its output will be given as.
By using k-map we get
f =  m (1,3,4,6 )

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 Combinational Logic Circuits

By using k-map we get 11. (a)

We know that
D0 → MSB
D3 → LSB
we can see that the given truth table is the truth table
f = xz + xz of priority encoder.
Hence, correct answer is option (b). V=0 is invalid output.
V=1 is valid output
Hence, correct answer is option (a).

❑❑❑

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 Design of springs

CHAPTER

4
Flip Flops (c) Q1Q0 after the 3rd cycle are 00 and after the 4th
cycle are 11 respectively
1. [MCQ] [GATE-2023: 1M] (d) Q1Q0 after the 3rd cycle are 01 and after the 4th
The output of a 2-input multiplexer is connected back cycle are 01 respectively.
to one of its inputs as shown in the figure. 3. [MCQ] [GATE-2015: 1M]
A positive edge-triggered D flip-flop is connected to
a positive edge-triggered JK flip-flop as follows. The
Q output of the D flip-flop is connected to both the J
and K inputs of the JK flip-flop, while the Q output of
the JK flip-flop is connected to the input of the D flip-
flop. Initially, the output of the D flip-flop is set to
logic one and the output of the JK flip-flop is cleared.
Match the function equivalence of this circuit to one Which one of the following is the bit sequence
of the following options. (including the initial state) generated at the Q output
(a) D Flip-flop (b) D Latch of the JK flip-flop when the flip-flops are connected
(c) Half-adder (d) Demultiplexer to a free-running common clock? Assume that J = K
= 1 is the toggle mode and J = K = 0 is the state-
2. [MCQ] [GATE-2017: 1M]
holding mode of the JK flip-flop. Both the flip-flops
Consider a combination of T and D flip-flops have non-zero propagation delays.
connected as shown below. The output of the D flip-
(a) 0110110... (b) 0100100...
flop is connected to the input of the T flip-flop and the
(c) 011101110... (d) 011001100...
output of the T flip-flop is connected to the input of
the D flip-flop. 4. [MCQ] [GATE-2014: 1M]

J Q2 J Q1 J Q0
T Q1 D Q0 C C C
Flip– Flip– K Q2 K Q1 K Q0
Flop Flop

Clock The above synchronous sequential circuit built using

Initially, both Q0 and Q1 are set to 1 (before the 1st JK flip-flops is initialized with Q2Q1Q0 = 000. The
clock cycle). The outputs state sequence for this circuit for the next 3 clock
(a) Q1Q0 after the 3rd cycle are 11 and after the 4th cycles is
cycle are 00 respectively (a) 001, 010, 011 (b) 111, 110, 101
(b) Q1Q0 after the 3rd cycle are 11 and after the 4th (c) 100, 110, 111 (d) 100, 011, 001
cycle are 01 respectively

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 Sequential Circuits

5. [MCQ] [GATE-2011: 1M]

The minimum number of D flip-flops needed to D Q
P
design a mod-258 counter is
Clock Q
(a) 9 (b) 8
(c) 512 (d) 258 Q
D Q
6. [MCQ] [GATE-2011: 1M] Clock Q

Consider the following circuit involving three D-type

flip-flops used in a certain type of counter D Q R
configuration. If all the flip-flops were reset to 0 at Clock Q
power on, what is the total number of distinct outputs
(states) represented by PQR generated by the
counter? (a) 000 (b) 001
(c) 010 (d) 011

8. [MCQ] [GATE-2008: 1M]

P
D Q Consider the following state diagram and its
realization by a JK flip flop
Clock Q
01,10
00,11 00,11 J Q
Combinational
0 1
Q x
cicuit
y
D Q 01,10 K

Clock Q
CLK

The combinational circuit generates J and K in terms

of x, y and Q. The Boolean expressions for J and K
are:
D Q R (a) (x  y) 'and (x  y) ' (b) ( x  y ) 'and x  y
(c) x  y and ( x  y ) ' (d) x  y and x  y
Clock Q
Asynchronous Counter
9. [MCQ] [GATE-2010: 1M]
(a) 3 (b) 4 In the sequential circuit shown below, if the initial
(c) 5 (d) 6 value of the output Q1Q0 is 00,what are the next four
values of Q1Q0?
7. [MCQ] [GATE-2011: 1M]
1 T Q T Q
Consider the following circuit involving three D-type
flip-flops used in a certain type of counter Clock
configuration.
If at some instance prior to the occurrence of the clock Q0 Q1
edge, P, Q and R have a value 0, 1 and 0 respectively, (a) 11, 10, 01, 00 (b) 10, 11, 01, 00
what shall be the value of PQR after the clock edge? (c) 10, 00, 01, 11 (d) 11, 10, 00, 01

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 Digital Logic

Synchronous Counter 13. [NAT] [GATE-2018: 1M]

10. [MCQ] [GATE-2023: 2M] Consider the sequential circuit shown in the figure,
where both flip-flops used are positive edge-triggered
Consider a sequential digital circuit consisting of T
D flip-flops.
flip-flops and D flip-flops as shown in the figure.
CLKIN is the clock input to the circuit. At the
beginning, Q1, Q2 and Q3 have values 0, 1 and 1,
respectively.
The number of states in the state transition diagram of
this circuit that have a transition back to the same state
on some value of "in" is ______

14. [MCQ] [GATE-2017: 1M]

The next state table of a 2-bit saturating up-counter is
Which one of the given values of (Q1, Q2, Q3) can given below.
NEVER be obtained with this digital circuit? Q1 Q0 Q1 + Q0+

(a) (0, 0, 1) (b) (1, 0, 0) 0 0 0 1

(c) (1, 0, 1) (d) (1, 1, 1) 0 1 1 0
1 0 1 1
1 1 1 1
11. [MCQ] [GATE-2021: 1M]
The counter is built as a synchronous sequential
Consider a 3-bit counter, designed using T flip-flops,
as shown below. circuit using T flip-flops.
The expressions for T1 and T0 are

(a) T = Q Q , T = ̅̅̅̅
𝑄1 ̅̅̅̅
𝑄0
1 1 0 0

(b) T = ̅̅̅
Q Q , T = ̅̅̅̅
𝑄1 + ̅̅̅̅
𝑄0
1 1 0 0

(c) T = Q +Q , T = ̅̅̅̅
𝑄1 + ̅̅̅̅
𝑄0
Assuming the intial state of the counter given by PQR 1 1 0 0

as 000. What are the next three states? (d) T = ̅̅̅

Q Q , T = 𝑄1 + 𝑄0
1 1 0 0
(a) 011,101,000 (b) 001,010,111
(c) 011,101,111 (d) 001,010,000
15. [MCQ] [GATE-2015: 1M]
12. [MCQ] [GATE-2021: 2M] Conisder a 4-bit Johnson counter an initial value of
The minimum number of JK flip-flops requried to 0000. The counting sequence of this counter is-
construct a synchronous counter with the count (a) 0,1,3,7,15,14,12,8,0
sequence (0,0,1,1,2,2,3,3,0,0….)is . (b) 0,1,3,5,7,9,11,13,15,0
(c) 0,2,4,6,8,10,12,14,0
(d) 0,8,12,14,15,7,3,1,0

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 Sequential Circuits

16. [MCQ] [GATE-2014: 1M] 17. [MCQ] [GATE-2009: 1M]

Let k = 2n. A circuit is built by giving the output of an How many 32K × 1 RAM chips are needed to
n-bit binary counter as input to an n-to-2n bit decoder. provide a memory capacity of 256K-bytes?

This circuit is equivalent to a (a) 8 (b) 32

(c) 64 (d) 128
(a) k-bit binary up counter.
(b) k-bit binary down counter. Memoery
(c) k-bit ring counter. 18. [MCQ] [GATE-2012: 00M]
(d) k-bit Johnson counter. The amount of ROM needed to implement a 4 bit
multiplier is
(a) 64 bits (b) 128 bits
(c) 1 Kbits (d) 2 Kbits

❑❑❑

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 Digital Logic

1. (b) 2. (b) 3. (a) 4. (c)

5. (a) 6. (c) 7. (d) 8. (d)
9. (a) 10. (a) 11. (a) 12. (3)
13. (2) 14. (b) 15. (d) 16. (c)
17. (c) 18. (d)

1. (b) Clock Q1 Q0
0 1 1
1 0 1
0=S Q 2 1 0
3 1 1
P 1=S 4 0 1
S 5 1 0
6 1 1
S from above table the output state after 3rd and 4th
clock pulse are 11 (Q1Q0) & 01 (Q1Q0) respectively
Qn+1 = Q S + DS
hence correct option is (b).
Qn+1 = Q.0+D.1
Qn+1 = D
Qn+1 is generated after delay
Now in a flip flop we always consider edge
3. (a)
but in the circuit, it is level sensitive, therefore
the circuit is equivalent to a D-latch. According to the question, the given sequential
circuit will look like as follows.

2. (b)
Given present state of both flip flop before apply
clock pulse is High (i.e. 1)

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 Sequential Circuits

CLK Qn of JK Flip Flop to solve (i) by taking log on both sides we get,
0 0 n  log2 M
n  log2 258 [ M = 258]
1 1
n  8.01122
2 1
n9
3 0
Hence, correct answer is option (a).
4 1
5 1
From the above truth table the Output of JK Flip
Flop will be
6. (c)
0 → 1→1→0→1→1
As per the given conditions, the truth table will be
= 011011...
given as
Hence, correct answer is option (a).
CLOCK P Q R
0 0 0 0
1 0 1 0
2 0 1 1
3 1 0 0
4. (c) 4 0 0 0
The truth table of the given flip-flop will be We can see that the above truth table is the output of
a mod- 4 counter.
JK-flip flop
Hence total number of distinct states = 4
CLK Q2 Q1 Q0 Hence, correct answer is option (b)
0 0 0 0
1 1 0 0
2 1 1 0
3 1 1 1
7. (d)
From the above truth table, the state sequence for next
In the circuit PQR = 010
3 clock cycles are 100, 110 and 111.
Hence, correct answer is option (c). Before applying the clock, input of the Flip-flop
=011
So, in the D-FF whatever the inputs applied that will
come at the output along with clock.
So, output of counter = 011
5. (a) Hence, correct answer is option (d).
The number of Flip Flops needed to design Mod-M
counter,
M  2n …(i)
where n = number of flip flops

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 Digital Logic

8. (d) 9. (a)
We know that truth table of JK flip-flop is given by
+ → down
Qn Qn+1 J K
0 1 0 X 1 T Q T Q
0 1 1 X Clock
1 0 X 1
1 1 X 0
Q0 Q1
Now the truth table of given circuit is given by Asynchronous down counter
x y Qn Qn+1 J K The truth table of the above sequential circuit is
0 0 0 0 0 × given as follows.
0 0 1 1 × 0 CLK Q1 Q0
0 1 0 1 1 × 0 0 0
0 1 1 0 × 1 1 1 1
1 0 0 1 1 × 2 1 0
1 0 1 0 × 1 3 0 1
1 1 0 0 0 × 4 0 0
1 1 1 1 × 0 From the above truth table, we can see that it is an
Solving J & K using k-map, we get output of an Asynchronous down counter.
Hence, correct answer is option (a).

10. (a)
J = xy + xy = x  y
The characteristics table of given sequential
circuit

Clock T = Q3 D = Q1 T = Q2 Q1 Q2 Q3

0 - - - 0 1 1
1 0 0 1 0 0 0
K = xy + x y = x  y

Hence, correct answer is option (d). 2 1 0 0 1 0 0

3 1 1 0 0 1 0

4 1 0 1 1 0 1

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 Sequential Circuits

So, numebr of FF’s are = 3

5 0 1 0 1 1 1

6 0 1 1 1 1 0
7 1 1 1 0 1 1
From above table states involved 011, 000, 100,
010, 101, 111, 110. The only state 001 can never 13. (2)
be achieved. The characteristics table of given Flip-Flop
Hence correct answer is option (a).
Input D1 D2 Q1+ Q+2 (Out)
0 0 0 0 0
1 0 0 1 0
0 0 1 0 0
1 0 1 1 0
11. (a) 0 1 0 0 1
According to question , the initial state of counter is 1 1 0 1 1
PQR = 000 0 1 1 0 1
1 1 1 1 1
From above chracteristics table state transistion
diagram of the given positive edge-triggered D flip
flop is

From the truth table the next three states are

011→101→000

From above state transistion diagram after 2 state it

come back to some value.

12.. (3)

14. (b)
Q1 Q0 Q+ Q0+ T1 T0
0 0 0 1 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 0 0
For T0
Design the up counter of 3bit ignore the LSB.

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 Digital Logic

Now, according to question 2-bit binary counter is

T0 = Q1 + Q0 connected in the input of the above Decoder. The
For T1 output of the combination will be given as
A B y0 y1 y2 y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
T1 = Q1 Q0 1 1 0 0 0 1

Hence correct answer is option (b).

15. (d)

0 0 0 0→ 0
1 0 0 0→ 8
1 1 0 0→ 12
1 1 1 0→ 14
1 1 1 1→ 15
0 1 1 1→ 7
0 0 1 1→ 3
0 0 0 1→ 1

Ring counter of 2n bits i.e. k-bit ring counter.

Hence, correct answer is option (c)

16. (c)
Let 2 × 4 Decoder as shown below, be at the output

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 Sequential Circuits

17. (c) 18. (d)

Number of required chips for memory capacity
= 256 ×210 × 8
Number of available chips for RAM capacity
= 32 ×210 × 1
Input output
Now, 4 4
ROM = 2 2  2
Number of chips needed to build 256K-bytes will be
= 28× 23
Re quired 256  2  8
10
= 211
Number of chips = = = 64
Avaliable 32 × 210 = 2× 210
Hence, correct answer is option (c). = 2k bits

❑❑❑

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