Hardware Implementation of Assignment 2

Department of Electrical Engineering Spring Semester 2024 1
EEN - 611 FPGA-DSP

Lab Report
Shubhranshu Pandey
Mtech (power system)
23529011
I. TUTORIAL-5:HARDWARE IMPLEMENTATION OF ASSIGNMENT-2

1) Q.1- Write a verilog code for the logic gates AND, OR, NOT, NAND, NOR, XOR, XNOR and
verify with zedboard.
Code-
module a l l g a t e ( a , b , c , d , e , f , g , h , i ) ;
inputa,b;outputc,d,
e,f,g,h,i;
and a1 ( c , a , b ) ;
or a2 ( d , a , b ) ; n
o t a3 ( e , a ) ;
nand a4 ( f , a , b ) ;
nor a5 ( g , a , b ) ;
xor a6 ( h , a , b ) ;
xnor a7 ( i , a , b ) ;
endmodule
Circuit
Fig. 1. Circuit Diagram of all gates
2) Q-2.- Design a half adder and verify the performance through verilog code Code-
module Q u e s t i o n 2 ( a , b , s , c ) ; i
n p u t a , b ; o u t p u t s , c ; xor x1 ( s ,
a , b ) ; and a1 ( c , a , b ) ; endmodule
Zedboard
Tcl console output
Fig. 4. Time comparison between implementation and synthesis
3) Question 3- Design a 1-bit full adder and verify the performance through verilog code Code:-
module Q u e s t i o n 3 ( a , b , c in , s , c o u t ) ;
inputa,b,cin;
outputs,cout;
w i r e l , m, n ;
and a1 ( l , a , b ) ; and
a2 (m, b , c i n ) ; and
a3 ( n , c in , a ) ;
or o1 ( cout , l , m, n ) ;
xor x1 ( s , a , b , c i n ) ;
endmodule
Constraints
Circuit
Fig. 6. Circuit Diagram of Half Adder
4) Question-4 Develop a 1-bit full adder verilog module using the half adder verilog modules
Code-
module ha ( a , b , s , c ) ; i
nputa,b;outputs,c
; xor x1 ( s , a , b ) ; and a1
( c , a , b ) ; endmodule
module f a h a ( a , b , c in , s , c o u t ) ; i n
puta,b,cin;outputs,cout;wire
s1 , c1 , c2 ;
ha ha1 ( . a ( a ) , . b ( b ) , . s ( s 1 ) , . c ( c1 ) ) ;
ha ha2 ( . a ( s 1 ) , . b ( c i n ) , . s ( s ) , . c ( c2 ) ) ;
or o1 ( c out , c1 , c2 ) ; endmodule
Zedboard
Zedboard
Tcl console output
5) Question5- Design and develop a 16-bit ripple carry adder verilog module using the 4-bit full
adder modules from .
Code-
module F u l l A d d e r (
inputa,in
putb,inpu
t c in , o u t p u
t sum ,
outputcout
);
a s s i g n sum = a ˆ b ˆ c i n ;
a s s i g n c o u t = ( a & b ) | ( b & c i n ) | ( a & c i n ) ; endmodule
module R i p p l e C a r r y A d d e r 1 6 b i t ( i n
p u t [ 1 5 : 0 ] A, i n p u t [ 1 5 : 0 ] B , o u t
p u t [ 1 5 : 0 ] sum
Constraints
Fig. 10. Constraints of Half Adder
);
wire[15:0]carry;
F u l l A d d e r FA0 (
. a (A[ 0 ] ) ,
.b(B[0]),
. c i n ( 1 ’ b0 ) ,
. sum ( sum [ 0 ] ) ,
.cout(carry[0])
);
genvari;
generate
for(i=1;i < 16;i= i+1)begin:genf ull addersFullA
d d e r FA(
. a (A[ i ] ) ,
. b ( B[ i ] ) ,
.cin(carry[i−1]),
Circuit
Fig. 11. Circuit Diagram of 1-bit Full Adder
. sum ( sum [ i ] ) ,
.cout(carry[i])
);
end
e n d g e n e r a t e endmodule
Testbench Code-
module Q u e s t i o n 5 t e s t b e n c h ;
reg[3:0]a,b;
wire[3:0]s;
wirecout;
Question5uut(.a(a),.b(b),.s(s),.cout(cout));in
itialbegin
$ m o n i t o r ( $time , ” a=%b , b=%b , s=%b , c o u t=%b ” , a , b , s , c o u t ) ;
#5 a =4 ’ b0000 ; b =4 ’ b0000 ;
#5 a =4 ’ b0001 ; b =4 ’ b0001 ;
#5 a =4 ’ b0010 ; b =4 ’ b0010 ;
#5 a =4 ’ b0011 ; b =4 ’ b0011 ;
#5 a =4 ’ b1000 ; b =4 ’ b1000 ;
#5 $ f i n i s h ; end
Zedboard
Output
endmodule
6) Question-6 Design a 4-bit prime number detector and write a verilog structural module and
verify it using zedboard
Code-
module p r i m e n u m b e r d e t e c t o r ( a , o u t ) ;
input[3:0]a;o
utputout;wir
e l , m, n ; w i r e p ,
q,r,s;
n o t n1 ( l , a [ 3 ] ) ; n
o t n2 (m, a [ 2 ] ) ; n o
t n3 ( n , a [ 1 ] ) ;
and a1 ( p , l , a [ 0 ] ) ; and a2 (
q , l , m, a [ 1 ] ) ; and a3 ( r , m,
a [ 1 ] , a [ 0 ] ) ; and a4 ( s , n ,
a[1],a[0]);
or o1 ( out , p , q , r , s ) ;
endmodule
Constraints
Fig. 14. Constraints of 1-bit Full Adder
]
Circuit
Fig. 15. Circuit Diagram of 1-bit Full Adder using the half adder
7) Question7-Design and verify the 4 × 1 multiplexer function through verilog structural module
and verify it through zedboard.
Code-
module Q u e s t i o n 7 ( y , i , s ) ; i
nput[0:3]i;input[0:1]s;
outputy;
w i r e l , m, p , q , r , t ;
n o t g1 ( l , s [ 1 ] ) ; n o
t g2 (m, s [ 0 ] ) ;
and a1 ( p , s [ 1 ] , s [ 2 ] , i [ 3 ] ) ;
and a2 ( q , l , s [ 0 ] , i [ 2 ] ) ; and a3
( r , m, s [ 0 ] , i [ 1 ] ) ; and a4 ( t , l ,
m, i [ 0 ] ) ;
or o1 ( y , p , q , r , t ) ;
endmodule
Zedboard
Zedboard
Output
8) Question8- Design a 3 × 8 line decoder and verify the performance through zedboard..
Code
module t h r e e t o e i g h t d e c o d e r ( i n p
utx,y,z,
output [0:7]d
) ; and a1 ( d [ 0 ] , ˜ x , ˜ y , ˜ z
) ; and a2 ( d [ 1 ] , ˜ x , ˜ y , z )
; and a3 ( d [ 2 ] , ˜ x , y , ˜ z ) ;
and a4 ( d [ 3 ] , ˜ x , y , z ) ;
and a5 ( d [ 4 ] , x , ˜ y , ˜ z ) ;
and a6 ( d [ 5 ] , x , ˜ y , ˜ z ) ;
and a7 ( d [ 6 ] , x , y , ˜ z ) ;
and a8 ( d [ 7 ] , x , y , z ) ; endmodule
Constraints
Fig. 19. Constraints of 1-bit Full Adder
9) Question-9 Design a full- subtractor with half subtractor verilog modules
Code-
module f u l l s u b t r a c t o r ( a , b , c , d , b out ) ;
inputa,b,c;ou
t p u t d , b out ; w i
r e c1 , c2 , c3 ;
h a l f s u b t r a c t o r hs 1 ( . a ( a ) , . b (
b ) , . d ( c1 ) , . b out ( c2 ) ) ; h a l f s u b t r a
c t o r hs 2 ( . a ( c1 ) , . b ( c ) , . d ( d ) , . b out
( c3 ) ) ;
or o1 ( b out , c3 , c2 ) ;
endmodule
module h a l f s u b t r a c t o r ( a , b , d , b out ) ;
i n p u t a , b ; o u t p u t d , b out ; xor x1
(d,a,b);
and a1 ( b out , ˜ a , b ) ; endmodule
Testbencg Code-
module f u l l subtractor tb;
Circuit Diagram
Fig. 20. Circuit Diagram of 4-bit Ripple Carry Adder
rega,b,c;
w i r e d , b out ;
f u l l s u b t r a c t o r u u t ( . a ( a ) , . b ( b ) , . c ( c ) , . d ( d ) , . b out ( b out ) ) ;
initialbegin
$ m o n i t o r ( $time , ” a=%b , b=%b , c=%b , d=%b , b out=%b ” , a , b , c , d , b out ) ;
#5 a =1 ’ b0 ; b =1 ’ b0 ; c =1 ’ b0 ;
#5 a =1 ’ b0 ; b =1 ’ b0 ; c =1 ’ b1 ;
#5 a =1 ’ b0 ; b =1 ’ b1 ; c =1 ’ b0 ;
#5 a =1 ’ b0 ; b =1 ’ b1 ; c =1 ’ b1 ;
#5 a =1 ’ b1 ; b =1 ’ b0 ; c =1 ’ b0 ;
#5 a =1 ’ b1 ; b =1 ’ b0 ; c =1 ’ b1 ;
#5 a =1 ’ b1 ; b =1 ’ b1 ; c =1 ’ b0 ;
#5 a =1 ’ b1 ; b =1 ’ b1 ; c =1 ’ b1 ;
#5 $ f i n i s h ;
end endmodule
Circuit
Diagram
Fig. 21. Circuit Diagram of prime number detector
10) Q-10 Design a seven segment display and verify the performance through the verilog code with
case statements
Code:-
module Seven segment (

i n p u t w i r e [ 3 : 0 ] number , o u t
p u t r e g [ 6 : 0 ] segments
);
a lways @( * ) b e g i n c a
s e ( number )
4 ’ b0000 : segments = 7 ’ b1000000 ; // 0
4 ’ b0001 : segments = 7 ’ b1111001 ; // 1
4 ’ b0010 : segments = 7 ’ b0100100 ; // 2
4 ’ b0011 : segments = 7 ’ b0110000 ; // 3
4 ’ b0100 : segments = 7 ’ b0011001 ; // 4
4 ’ b0101 : segments = 7 ’ b0010010 ; // 5
4 ’ b0110 : segments = 7 ’ b0000010 ; // 6
4 ’ b0111 : segments = 7 ’ b1111000 ; // 7
4 ’ b1000 : segments = 7 ’ b0000000 ; // 8
Zedboard
Zedboard
Output
4 ’ b1001 : segments = 7 ’ b0010000 ; //9

4 ’ b1010 : segments = 7 ’ b0001000 ; //A
4 ’ b1011 : segments = 7 ’ b0000011 ; //B
4 ’ b1100 : segments = 7 ’ b1000110 ; //C
4 ’ b1101 : segments = 7 ’ b0100001 ; //D
4 ’ b1110 : segments = 7 ’ b0000110 ; //E
4 ’ b1111 : segments = 7 ’ b0001110 ; //F
d e f a u l t : segments = 7 ’ b1111111 ; / / Turn o f f a l l segments
endcase
end
endmodule
Constraints
Fig. 25. Constraints of prime number detector

Zedboard
Zedboard
Output
Circuit Diagram
Fig. 29. Circuit Diagram of 4 to 1 mux

Zedboard
Zedboard
Output
Circuit Diagram
Fig. 33. Circuit Diagram of 3 to 8 line decoder
Constraints
Fig. 34. Constraints of 3 to 8 line decoder

Zedboard
Zedboard output
Output
Fig. 37. Tcl console output of full- subtractor

Circuit Diagram
Fig. 38. Circuit Diagram of full- subtractor

Zedboard
Zedboard
Output
Fig. 41. Time comparison between implementation and synthesiss
Constraints
Fig. 42. Constraints of 4 × 1 multiplexer with tristate buffers

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Department of Electrical Engineering Spring Semester 2024 1

EEN - 611 FPGA-DSP

I. TUTORIAL-5:HARDWARE IMPLEMENTATION OF ASSIGNMENT-2

Fig. 1. Circuit Diagram of all gates

Tcl console output

Fig. 4. Time comparison between implementation and synthesis

Fig. 6. Circuit Diagram of Half Adder

Tcl console output

Fig. 9. Time comparison between implementation and synthesis

Fig. 10. Constraints of Half Adder

Fig. 11. Circuit Diagram of 1-bit Full Adder

Fig. 13. Time comparison between implementation and synthesis

Fig. 14. Constraints of 1-bit Full Adder

Fig. 18. Time comparison between implementation and synthesis

Fig. 19. Constraints of 1-bit Full Adder

9) Question-9 Design a full- subtractor with half subtractor verilog modules

Fig. 20. Circuit Diagram of 4-bit Ripple Carry Adder

Fig. 21. Circuit Diagram of prime number detector

module Seven segment (

Fig. 24. Time comparison between implementation and synthesis

4 ’ b1001 : segments = 7 ’ b0010000 ; //9

Fig. 25. Constraints of prime number detector

Fig. 28. Time comparison between implementation and synthesis

Fig. 29. Circuit Diagram of 4 to 1 mux

Fig. 32. Time comparison between implementation and synthesis

Fig. 34. Constraints of 3 to 8 line decoder

Fig. 37. Tcl console output of full- subtractor

Fig. 38. Circuit Diagram of full- subtractor

Fig. 41. Time comparison between implementation and synthesiss

Fig. 42. Constraints of 4 × 1 multiplexer with tristate buffers

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