U18ECI6203 -

VLSI & HDL

Programming
Module 1 – Verilog HDL
Part 5 – Behavioural & Data flow modelling
Data flow modelling
• Describes the signal glow in a circuit.
• Keyword “assign” will be used.
• Example:
• Assign b=a+b;
• Assign x=y&z;
Half adder using Data flow modelling

Dataflow
module ha(a,b,s,c)
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule
Half adder using gate level & Data flow
modelling
Dataflow Gate level
module ha(a,b,s,c); module ha(a,b,s,c);
input a,b; input a,b;
output s,c; output s,c;
assign s=a^b; xor a1(s,a,b);
assign c=a&b; and a2(c,a,b);
endmodule endmodule
Half adder -
Behavioural
modelling – Using
case
Half adder -
Behavioural
modelling – Using
if else
Data flow modelling – Detailed concepts
Continuous assignment

07/28/2023 Verilog HDL 8

Implicit continuous assignment
Operators
Conditional operator
Behavioural modelling – Detailed concepts
• Structured procedures
• Initial
• Initial (begin, end)
• Always
• Procedural assignments (update values of reg, integer, real, or
time variables)
• Blocking assignment (=)
• Will be executed in the order how they are specified
• Non blocking assignment (<=)
• Will be executed parallel at time 0
Example (initial, always)
• Conditional statements
• If, else
• Else if
• Multi way branching
• Case statement
• casez treats all z values in the case alternatives or the case expression as
don't cares. All bit positions with z can also represented by ? in that
position.
• casex treats all X and z values in the case item or the case expression as
don't cares.
Encoder (without priority)
module encwtoutprio(a,en,y);
input [7:0] a;
input en;
output reg [2:0] y;
always@(a or en)
begin
if(!en)
y<=1'b0;
else
case(a)
8'b00000001:y<=3'b000;
8'b00000010:y<=3'b001;
8'b00000100:y<=3'b010;
8'b00001000:y<=3'b011;
8'b00010000:y<=3'b100;
8'b00100000:y<=3'b101;
8'b01000000:y<=3'b110;
8'b10000000:y<=3'b111;
endcase
end
endmodule
Encoder (with priority)
module priorityencoder(a,en,y);
input [7:0] a;
input en;
output reg [2:0] y;
always@(a or en)
begin
if(!en)
y<=1'b0;
else
casex(a)
8'b00000001:y<=3'b000;
8'b0000001x:y<=3'b001;
8'b000001xx:y<=3'b010;
8'b00001xxx:y<=3'b011;
8'b0001xxxx:y<=3'b100;
8'b001xxxxx:y<=3'b101;
8'b01xxxxxx:y<=3'b110;
8'b1xxxxxxx:y<=3'b111;
Endcase
end
endmodule
Tasks and functions
Task
Function
4 bit multiplier
Full Adder Module: Multiplier Module: (P[0],M[0],Q[0]);
module Full_Adder( module M4bit( Full_Adder fa1(c1,c2,c3,d2,d1);
input [3:0] Q, Full_Adder fa2(c4,c5,c6,d4,d3);
input x,y,cin; input [3:0] M, Full_Adder fa3(c7,c8,c9,d6,d5);
output s, cout; output [7:0] P Full_Adder fa4(c10,c11,0,P[1],d7);
); ); and(e1,M[2],Q[3]),
wire c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11; (e2,M[3],Q[2]),
wire c1,c2,c3; wire d1,d2,d3,d4,d5,d6,d7; (e3,M[0],Q[3]);
xor(s,x,y,cin); wire e1,e2,e3; Full_Adder fa5(e1,e2,d1,f2,f1);
and(c1,x,y), wire f1,f2,f3,f4,f5,f6,f7; Full_Adder fa6(d2,d3,f5,f4,f3);
wire g1,g2,g3,g4; Full_Adder fa7(d4,e3,d5,f6,f5);
(c2,x,cin),
and(c1,M[3],Q[1]), Full_Adder fa8(d6,d7,0,P[2],f7);
(c3,y,cin); (c2,M[2],Q[2]), and(g1,M[3],Q[3]);
or(cout,c1,c2,c3); (c3,M[1],Q[3]), Full_Adder fa9(g1,f1,g2,P[6],P[7]);
(c4,M[3],Q[0]), Full_Adder fa10(f2,f3,g3,P[5],g2);
endmodule
(c5,M[2],Q[1]), Full_Adder fa11(f4,0,g4,P[4],g3);
(c6,M[1],Q[2]), Full_Adder fa12(f6,f7,0,P[3],g4);
(c7,M[2],Q[0]), Endmodule
(c8,M[1],Q[1]),
(c9,M[0],Q[2]),
(c10,M[1],Q[0]),
(c11,M[0],Q[1]),
D flipflop
D flipflop
Sync counter
Async counter
Counter
Up-Down counter