Assignment 01

Name: Naman Rana

Course: M.Tech

Department: Electronics(VLSI DESIGN)

SID: 23215005

Subject: Computer Aided VLSI Design

Submitted to:
Dr. Neelam Rup Prakash
 1. Combinational Circuits

1. AND Gate
2. 4x1 Multiplexer
3. Full Adder
4. Full Subtractor
5. Priority Encoder(4:2)

Ans 1. : AND Gate(dataflow style) module

andgate(input a, input b, output y);

assign y = a&b;

endmodule

AND Gate(structural style) module

AND_2(output Y, input A, B);

and(Y, A, B); endmodule

AND Gate(behavioral style) module AND_2_behavioral (output

reg Y, input A, B); always @ (A or B) begin if (A == 1'b1 & B == 1'b1)

begin

Y = 1'b1;

end

else

Y = 1'b0; end

endmodule

Ans 2. : 4x1 Multiplexer(behavioral style)

module mux4x1(input a, input b, input c, input d, input sa0, input sa1,

output y);

always@(sa0 and sa1)

 begin

if((sa0==0)&(sa1==0))

y = a;

if((sa0==0)&(sa1==1))

y = b;

if((sa0==1)&(sa1==0))

y = c;

if((sa0==1)&(sa1==1))

y = d;

end

endmodule

4x1 Multiplexer(Structural style) module m41(out,

a, b, c, d, s0, s1);

output out; input a, b, c, d, s0, s1;

wire sobar, s1bar, T1, T2, T3, T4;

not (s0bar, s0), (s1bar, s1);

and (T1, a, s0bar, s1bar), (T2, b, s0bar, s1),(T3, c, s0, s1bar), (T4, d, s0, s1);
or(out, T1, T2, T3, T4);

endmodule
4x1 Multiplexer(Dataflow Style) module m41
( input a,

input b,

input c,

input d,

input s0, s1,

output out);

assign out = s1 ? (s0 ? d : c) : (s0 ? b : a);

 endmodule

4x1 Multiplexer(Structural style) module m41(out,

a, b, c, d, s0, s1);

output out; input a, b, c, d, s0, s1;

wire sobar, s1bar, T1, T2, T3, T4;

not (s0bar, s0), (s1bar, s1);

and (T1, a, s0bar, s1bar), (T2, b, s0bar, s1),(T3, c, s0, s1bar), (T4, d, s0, s1);
or(out, T1, T2, T3, T4);

endmodule
4x1 Multiplexer(Dataflow Style) module m41
( input a,

input b,

input c,

input d,

input s0, s1,

output out);

assign out = s1 ? (s0 ? d : c) : (s0 ? b : a);

endmodule

Ans 3: Full Adder (dataflow style)

module full_adder(a,b,cin,sum, cout);

input a,b,cin; output sum, cout; assign sum

= a^b^cin; assign cout =

((a&b)|(b&c)|(c&a));

endmodule

Full Adder (Structural Style) module

full_adder_s (

input a,b,cin, output

sum,carry

);

wire w1,w2,w3,w4; //Internal connections xor(w1,a,b); xor(sum,w1,cin); //Sum output

and(w2,a,b); and(w3,b,cin);

and(w4,cin,a);

or(carry,w2,w3,w4); //carry output

endmodule

Ans 6: Full Subtractor(DataFlow Style) module

Full_Subtractor_3(output D, B, input X, Y, Z); assign D = X ^ Y ^ Z;

assign B = ~X & (Y^Z) | Y & Z; endmodule

Full Subtractor(Structural Style)

module full_subtractor(

input a,
input b,
input c,

output diff
output borr); wire
x,n2,z,n1; xor
s1(x,a,b); not
s3(n2,x); not
s4(n1,c); and
s5(y,n1,b); xor
s2(diff,a,x); and
s6(z,n2,a); or
(borr,y,z);

endmodule

Ans 7: 4:2 Priority encoder(structural)

module priority_encoder_42(A0,A1,Y0,Y1,Y2,Y3);

input Y3, Y2, Y1, Y0; output A0,

A1;

wire y2bar; //not of y2 wire and_out;

// and of y2bar and y1 not(y2bar, y2);

and(and_out, y2bar, y1); or(A1, Y3, Y2); or(A0,

and_out, Y3); endmodule

4:2 Priority Encoder(dataflow) module

priority_encoder_datafloe(A0,A1,Y0,Y1,Y2,Y3); input Y0,Y1,Y2,Y3;

output A0,A1;

assign A1 = Y3 + Y2; assign A0

= Y3 + ((~Y2)&Y1); endmodule

2. Sequential Circuits

1. T Flip Flop
2. J-K Flip Flop
3. S-R Flip Flop
4. D- Flip Flop
5. SR Latch
Ans 1: T-FF(Behavioral)

module TFF (

input logic T, clk, rst, output

logic Q, Qn

);

always_ff @(posedge clk, posedge rst) begin if (rst)

begin

Q <= 0;

Qn <= 1;

end else if (T) begin

Q <= ~Q;

Qn <= Q; end end

endmodule T-FF(Structural)

module tff_gate_level (

input clk,

input t, output

reg q

);

wire n1, n2, n3, n4;

not (n1, t); not (n2, clk);

nand nand1 (n3, n1, q);

nand nand2 (n4, n2, n3);

nand nand3 (q, n4, q);

endmodule

T-FF (DataFlow Style)

Not Possible as T flip flop doesn’t work on level triggered clock Ans 2: JK-FF(Behavioral) module jkff

( input logic J, K, clk, rst, output logic Q, Qn

);

always_ff @(posedge clk, posedge rst) begin if (rst)

begin

Q <= 0;

Qn <= 1; end else if (J && K)

begin

Q <= ~Q;

Qn <= Q; end else if

(J) begin

Q <= 1;

Qn <= 0; end else if

(K) begin

Q <= 0;
Qn <= 1;

end

end

endmodule

JK-FF(Dataflow)

Not Possible as JK flip flop doesn’t work on level triggered clock JK-

FF(Structural) module jkff_gate(q,qbar,clk,j,k);

input j,k,clk; output

q,qbar; wire

nand1_out; // output

from nand1 wire

nand2_out; // output

from nand2
nand(nand1_out, j,clk,qbar); nand(nand2_out,

k,clk,q); nand(q,qbar,nand1_out);

nand(qbar,q,nand2_out);

endmodule

Ans 3: SR-FF(Behavioral)

module SRFF (

input logic S, R, clk, rst, output

logic Q, Qn

);

always_ff @(posedge clk, posedge rst) begin if (rst)

begin

Q <= 0;

Qn <= 1; end else if

(S) begin

Q <= 1;

Qn <= 0;

end else if (R) begin

Q <= 0;

Qn <= 1;

end end

endmodule

SR-FF(Dataflow)
Not Possible as SR flip flop doesn’t work on level triggered clock

SR-FF(Structural) module srff_gate(q,

qbar, s, r, clk);
input s,r,clk; output q,

qbar;

wire nand1_out; // output of nand1 wire

nand2_out; // output of nand2

nand (nand1_out,clk,s); nand

(nand2_out,clk,r); nand

(q,nand1_out,qbar); nand

(qbar,nand2_out,q);

endmodule

Ans 4: D-FF(Structural)

module nand_gate(c,a,b);

input a,b; output c;

assign c = ~(a&b);

endmodule

module not_gate(f,e);

input e; output f;

assign f= ~e;

endmodule

module d_ff_struct(q,qbar,d,clk);

input d,clk; output q, qbar; not_gate

not1(dbar,d); nand_gate

nand1(x,clk,d); nand_gate

nand2(y,clk,dbar); nand_gate
nand3(q,qbar,y); nand_gate

nand4(qbar,q,x); endmodule

D-FF(Behavioral) module
dff_behavioral(d,clk,clear,q,qbar); input d, clk,

clear; output reg q, qbar; always@(posedge

clk) begin if(clear== 1) q <= 0; qbar <= 1; else q

<= d; qbar = !d; end endmodule

D-FF(Dataflow)

Not Possible as D flip flop doesn’t work on level triggered clock

Ans 5: SR- Latch(Structural)

module sr_latch (

output Q, input R,

input S

);

// Instantiate NOR gates

wire sn, rn, qn; nor n1 (Q,

sn, Qn); nor n2 (Qn, Q, rn);

nor n3 (sn, S, ~Qn); nor n4

(rn, R, ~Q);

endmodule

SR- Latch(Behavioral)
module sr_latch ( output Q,

input R, input S

);
always @(R or S) begin case

({R, S})

2'b00: Q <= Q; // Hold current state

2'b01: Q <= 1; // Set latch

2'b10: Q <= 0; // Reset latch

2'b11: Q <= X; // Invalid condition (undefined output)

endcase end

endmodule

SR- Latch(Dataflow)
Cannot be implemented as dataflow considers combinational circuits

3. Logic Synthesis Questions

1. Design a logic circuit using XOR gates to generate the even parity of a 4-bit input
(D0, D1, D2, D3). The output should be 0 if the number of 1s in the input is even,
and 1 if it's odd.
Ans: Assume 4bit number given to us. If we implement it in the form of F=(D0^D1)^(D2^D3).
It will produce 1 if number of zeroes is odd else 0.
 1. Implement a 3-bit shift register using D flip-flops and combinational logic. The
register should shift its contents to the right on each rising edge of the clock signal.
Consider how to handle data input and the most significant bit (MSB) shifting out.

Ans:

Here the logic Synthesis has been performed using the following code in Verilog
and schematic simulated on Vivado module shift_register(input clk, input shift_in,
input load, output [2:0] q);

// Instantiate D flip-flops d_flip_flop d0(.clk(clk),.d(load

? shift_in : q[1]), .q(q[0])); d_flip_flop d1(.clk(clk),
.d(load ? q[0] : q[2]), .q(q[1])); d_flip_flop d2(.clk(clk),
.d(load ? q[1] : shift_in), .q(q[2]));

endmodule

// Define D flip-flop module (optional)

Module d_flip_flop(input clk,

Input d, output q); reg q_reg;

always @(posedge clk)

begin
 q_reg <= d;

end assign q =

q_reg;

endmodule