25. Design MOD 12 asynchronous counter and draw the timing diagram.

Reg. No.
26. Draw the schematic diagram of XOR gate using transmission gates.

27. Design 4-bit binary to gray code convertor by using ROM. B.Tech. DEGREE EXAMINATION, NOVEMBER 2016
Third Semester
PART- C (5 x 12 - 60 Marks)
Answer ALL Questions I5EC2O3J _ DIGITAL SYSTEMS
(For the candidates admitted during the academic year 2015 - 2016 onwards)
Note:
28. a. Implement 2's complement circuit for 4-bit binary number by using universal gates. (D Parl - A should be answered in OMR sheet within first 45 minutes and OMR sheet should be handed
over to hall invigilator at the end of 45t minute.
(oR) (ii) Part - B and Part - C should be answered in answer booklet.
b. Simplify the following Boolean function by usi,ng Quine Mc-cluskey method
F (A, B,C, D) - Zm(O,2,3,6, 7, 8, 1 0, 12, 1 3). Time: Three Hours Max. Marks: 100

29. a. Explain the operation of CMOS inverter, NAND gate and NOR gates.
PART-A (20 x I :20 MarL.s)
Answer ALL Questions
(oR) 1. Excess-3 code is known as
b. Explain the working of two input NAND gate totem-pole circuit. (A) Weighted code (B) Redundancycode
(C) Self-complementary code (D) Algebraic code
30. a. Design a4-bit magrritude comparator. 2. How many l's are present in the binary representation 15x256+5x16+3?
(A) 8 (B) e
(oR) (c) 10 (D) 11
b. Draw the schematic diagram for an even parity generator and checker by using IC74180.
Design and draw the logic diagram ofan even parity generator and odd parity generator for 4
3. Assuming that only the X and Y logic inputs are available and their competent X and 7 are
bit data- not available, what is the minimum number of two input NAND gate require to implement
x@Y?
31. a. Design and implement a synchronous decade counter using T-flip flop. Draw timing (A) 2 (B) 3
diagram. (c) 4 (D) s
4. The minterrns corresponding to decimal number 15
(oR) (A) ABCD (B) AEED
b. Design and implement a sequential circuit that generates the sequence 0,7,2,4,3,6,7,0.... (c) ,s+E+c+D (D) z+B+C+D
(Use JK flip flop for design). \_
i 5. The fast logic family is
(A) ECL (B) TrL
32. a. Design BCD -Excess-3 convertor using PAL. (c) rRL (D) DRL
(oR) 6. Which logic family provide minimum power dissipation?
b. Design a combinational circuit using PLA. The circuit accepts 3 bit and generates an output (A) rrl. (B) CMOS
binary equal to square of input number. (c) ECL (D) JFET
7. The output Y of the circuit shown below
Ycc
***** --.1A

a-l
n ---.1

c-l
(A) t*E*c (B) A+B+C
(c) ABe (D) ,qEc
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 15. A MOD 16 ripple counter is holding the count (1001), what will the count be after 32 clock
8. In the circuit shown Dr, Dz, D: are ideal and inputs E1, E2, E3 are 0V for logic 0 and 10V for pulse?
Iogic 1, what logic gates does the circuit represents, (A) (1001), (B) (1011),
Et
(c) (1000h (D) (llll),
16. The circuit shown consists of JKFF's, each with an active low asynchronous reset, the
E2 counter corresponding to this circuit is

E3

I
(A) 3 input OR gate (B) 3 inputNOR gate
(A) MOD-5 binary up counter (B) MOD-6 binary down counter
(C) MOD-5 binary down counter (D) MOD-6 binary up counter
(c) 3 input AND gate (D) 3 inputNAND gate
t7. Which of the following memories uses one transistor and one capacitor as basic memory
9. FA can be implemented with HA and OR gate, 4 bit parallel adder without any initial carry unit?
requires (A) SRAM (B) DRAM
(A) 8HA 4ORgate (B) 8 IIA 3 OR gate (C) BothDRAM, SRAM (D) ROM
(C) 7HA 4ORgate (D) 7 HA 3 OR gate
18. A 16 kB memory array is designed as square with an aspect ratio of one (number of rows is
10. The combinational logic circuit shown below has an output Q which is equal to the number of column). The minimum number of address line needed for the row
decoder is
C Io (A) 14 @)4
I I1
I2
(c) 13 (D) 7
I
1 I3 19. A nibble is equal to bits
(A) 1 (B) 2
AB (c) 4 (D) 8

(A) A@ B@C (B) ABC 20. The content of a simple programmable logic devices @LD) consists of
(c) A+ B+C (D) AOBOC (A) Fuse link arrays (B) Thousands of basic logic gates
(C) Advanced sequential logic functions (D) Thousands of basic gates and advanced
I l. Carry look ahead adder is frequently used for addition, because it sequential logic functions
(A) Is faster (B) Is more accurate
(C) Uses fewer logic gates (D) Costs high PART-B (5 x 4=20 Marks)
Answer AI{Y FIVE Questions
12. The output Y of a 2-bit comparator is logic 1 , whenever the 2-bit input A is greater than 2-bit 21. Convert the following number from one base to another (23 1.3)4 to base 7.
input B, the number of combinations for which the output is logic 1, is
(A) 4 (B) 6 22. Design I to 8 De-multiplexer using two 2 to 4 decoder.
(c) 8 (D) l0
23. Simplifie the Boolean expression (X +Y)(X + )') + XY + X .

13. In the toggle mode a JKIF has

(A) J:0, K:0 (B) J:l,K--1 24. Find the Boolean function realizedby the following circuit and its truth table.
(c) J:0,K:l (D) J:1,K:o 0\
14. How many FF are required to build
(A)
a binary counter circuit
(B) 6
to count from 0 to 1023? +> ,/ l>- 0
t-/
1
(c) 24 (D) l0
sl s2
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