Roll No..

Exam Code: J-22

Subject Code-2092
B. Tech. EXAMINATION

(Batch 2018-2020)
(Third Semester)
ELECTRONICS & COMM. ENGINEERING
ECE203T
Digital Electronics

Time: 3 Hours Maximum Marks: 70

Note: Attempt Five questions in all. Q. No. 1 is
compulsory and contain seven subparts each
of 2 marks. Attempt any otherfour questions
selecting one question from each of four
Units. All questions carry equal marks.

1. (i) Define EX-OR and EX-NOR logic gates

along with truth table symbol. 2
(it) Define the terms in context of logic
family 2
(a) fan in
(b) fanout
(2-31-19-0122) J-2092 P.T.O.
 (ii) Draw the half adder circuit
using logic 3. (a) Discuss the Tristate configuration with
gates.
neat diagram.
(iv) Define multiplexer and demultiplexer and
list their (b) Draw the schematic and explain the
use as
logic elements. 2 operation of CMOS inverter.
(v) Distinguish between Moore and Mealy
model.
2 Unit II
(vi) List various
types of A/D and D/A
converter. 4. (a) Explain the code converter. Design a gray
2
to binary code converter and realize. 6
(vii) Describe the types of
programmable logic
device. 2
(b) Minimize the four variable function

Unit I
s(A, B, C, D) =m(0, 1, 2, 5, 7,9, 13, 15)
2. Convert the following number from given base +d(8,11)
to other base as indicated : 14 using K-map. Realise the minimised
function using logic gates.
(i) (11101011) > (.. Octal 8

(ii) (11101011)2 (...pecimal 5. (a) Using Quine McCluskey method reduce

(ii) (658)g (... decimal the given function 8
(iv) (658)g(... .hexadecimal S(A, B, C, D) 2m(0,5, 7,8,9,10,11, 14, 15)
=

(v) (2AC5)Hex(.. decimal (b) What do you understand by SOP and

(vi) (32)10(G... BCD Code POS term? 2
(vii) (32)10 (... Excess3code
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 Unit IV
(c) Realise the
8. (a) Explain the working of R-2R ladder
s(A, B, C, D) =m(0, 1, 2,3, 11, 12,14, 15)
digital to analog (D/A) converter with
using 16 : 1 multiplexer.
nest and clean diagram.
Unit IlI (b) Explain the working principle of
successive approximation analog to digital
6. (a) Explain the procedure to convert one flip
(A/D) converter with neat diagram. 7
to another flip flop. Explain, how JK
flip-flop is converter into T flip-flop ?7 9. (a) Write technical notes on the following
(b) Draw the circuit diagrams of J/K and D PAL
(i)
flip-flop and explain their operation with
(ii) ROM.
truth tables. Also lists some applications (b) Discuss the features and functional blocks
of J/K and D flip-flop. of FPGA. 4
7. (a) Design a sequence detector to detect a (c) Explain the implementation of full adder
serial input sequence 1010. Draw its state using PLA. 4

diagram, state table, state assignment table

and final implemented circuit. 8

(b) Compare synchronous and asynchronous

counter. 3

(c) What is a state table ? Give an example.

3

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