PART – A (10 * 2 =20)

1. Determine (658.825)10 in octal and hexadecimal equivalent.

2. Define propagation delay.
3. Simplify the expression Z=AB+AB’ (A’C’).
4. What are the applications of multiplexer and decoder.
5. State the rules for state assignment.
6. Show how the JK flip flop can be modified into a D flip flop or a T flip flop.
7. Draw the block diagram of PLA.
8. What is PROM?
9. Write the behavioral modeling code for a D flip flop.
10. State the advantage of package declaration over component declaration.
11. Convert the following binary code into a gray code 11012.
12. Define fan in and fan out
13. Design a Half subtractor.
14. Simplify the following Boolean expressions to a minimum number of literals :XY+X̅ Z+YZ
15. Give the characteristic function and equation of SR flip flop
16. State any 2 differences on Moorey and Mealy state machines.
17. What is static and dynamic hazard?
18. State the differences between PROM, PLA and PAL
19. Give the syntax for VHDL architechture declaration.
20. Name the four important packages used in VHDL.

PART –B (5*13=65 )

21. a.(i) Encode the binary word 1101 into seven bit even parity Hamming code.
(ii) Compare the totem-pole output with open collector output.
(Or)
b. Simplify the expression using Quine McCluskey Method
f(a,b,c,d) =(0,1,2,3,8,9)

22. a.(i) Reduce the following using K-map F(A,B,C,D)=Σm (0,2,3,8,9,12,13,15).

(ii) Convert the given expression in standard POS form f(A,B,C)= (A+B)(B+C)(A+C)

(Or)
b. Reduce the following function using K-map techniques and implement using basic
gates F(A,B,C,D) = A̅ B̅ D +AC̅ D̅ +A̅ BC+BCD̅
23. a. Explain the operation of Master Slave JK flip-flop with logic diagram and timing
diagram.

(Or)

b.(i) Design a synchronous MOD-6 counter using clocked JK flip-flop with logic
diagram. .
(ii).Convert SR flip- flop into JK flip- flop.

24 (a) (ii) Implement the following boolean functions using PAL.

W (A, B,C,D) = Σ (2,12,13)
X (A,B,C,D) = Σ (7,8,9,10,11,12,13,14,15)
Y(A,B,C,D) = Σ (0,2,3,4,5,6,7,8,10,11,15)
Z (A, B, C,D) = Σ (1,2,8,12,13).
(Or)
(b) Design an asynchronous sequential circuit that has two inputs X 2 and X1 and one
output Z. When X1 =0,the output Z is 0 .The first change in X 2 that occurs while X1 is 1
will cause output Z to be 1.The output Z will remain 1 until X1 returns to 0.
25. (a)(i)write the VHDL program for 1 to 4 Demux using dataflow modeling.
(ii) Write a VHDL code for a half adder using data flow modeling.
(Or)
(b)(i)Explain in detail the RTL design procedure.
(ii)Write short note on test benches.
26. a.(i) ) Given that a frame with bit sequence 0110011 is transmitted it has been received
as 0100011. Determine the method of detecting the error using any one error
detecting code. (6)
(ii) With circuit schematic, explain the operation of a two input TTL NAND gate with
totem pole output. (7)
(Or)
b.(i)Simplify the following function using K-map f(a,b,c,d) = Ʃm(0,1,3,9,10,12,13,14)+
Ʃd (2,5,6,11). (6)
(ii) Explain Hamming code with an example. State its advantages over parity codes.
(7)

27.(a) Design a logic circuit to convert the 8421 BCD to excess 3 code. (13)

(Or)
b) (i) Design Full-subtractor circuit using two Half subtractor circuit with truth table
and logic diagram. (10)

(ii)Write the limitation of Half subtractor. (3)

28 a. Design a synchronous MOD-11 counter using clocked JK flip-flop with logic

diagram. (13)
(Or)
 b. (i) Draw and explain the operation of serial in serial out shift register. (7)
(ii) Explain the operation of D flipflop with truth table and characteristic equation. (6)

29 a. What are the steps in the analysis and design of asynchronous sequential circuits?
Explain with an example. (13)
(Or)
b. A combinational circuit is defined by functions.
F1(A,B,C)= Ʃm(3,5,6,7)
F2(A,B,C)= Ʃm(0,2,4,7)
Implement the circuit with a PLA having three input , four product terms and two
outputs. (13)

30. a Write the VHDL code to realize full adder using behavioural approach. (13)

(Or)
(b) (i)Briefly discuss the packages used in VHDL. (7)

(ii)Write VHDL code using dataflow modeling for 4:1 MUX. (6)

PART –C (1*15=15 )
31. a. Design a Half adder and Full adder circuit with truth table and logic diagram. (15)
(Or)
b. Give the hazard free realization for the following Boolean functions. (15)
(i) F(A,B,C,D)=Ʃm (1,3,5,7,8,9,14,15)
(ii) F(A,B,C,D)= Ʃm (1,3,4,5,6,7,9,11,15)

32. a. Design a CMOS inverter and explain its operation. Comment on its characteristics such
as Fan in, Fan out, power dissipiation, propagation delay and noise margin. Compare its
advantages over other logic families. (15)

(OR)
b.(i)Explain the parallel in serial out shift register with neat diagram. (5)
(ii)Design a sequence generator to generate the sequence. 0 →2→ 5→ 4 →7→ 3→ 0
using JK flipflop. (10)