3-Ee8551-Microprocessors and Microcontrollers

Interrupts priority
TRAP 1
RST7.5 2
RST6.5 3
RST5.5 4
INTR 5
8.
8.What is the signal classification of 8085?
All the signals of 8085 can be classified into 6 groups
1 2
1.Address
. bus 2.Data
. bus
3 4
3.Control
. and status signals 4.Power
. supply and frequency signals
6
5.Externally
5 initiated signals 6.Serial
. I/O ports
9. Steps involved to fetch a byte in 8085?
i) The pc places the 16-bit memory address on the address bus

ii) The control unit sends the control signal RD to enable the memory
chip
iii) The byte from the memory location is placed on the data bus
iv) The byte is placed in the instruction decoder of the microprocessor and the task is
carried out according to the instruction.
10. Define instruction cycle,machine cycle and T-state?
Instruction cycle is defined as the time required completing the execution of an

instruction.
Machine cycle is defined as the time required completing one operation of accessing
memory,I/O or acknowledging an external request.T –cycle is defined as one subdivision of
the operation performed in one clock period.
11.How many machine cycles does 8085 have, mention them?

The 8085 have seven machine cycles they are
1 2
Opcode
. fetch Memory
. read
3 4
Memory
. write I/O. read
5 6
I/O .write Interrupt
. acknowledge
Bus idle
12.Steps involved to fetch a byte in 8085?
HOLD indicates that a peripheral such a DMA controller is requesting the use of
address bus, data bus and control bus.
READY is used to delay the microprocessor read or write cycles until a slow
responding peripheral is ready to accept or send data.
SID is used to accept serial data bit by bit.
13.Define flags?
The flags are used to reflect the data conditions in the accumulator.the 8085 flags are s-
sign flag,zero flag,auxillary flag,parity flag,
D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
14. Difference between memory mapped I/O and peripheral I/O ?

MEMORY MAPPEED I/O PERIPHERAL I/O
16-bit device address 8-bit device address
The data transfer between any general- The data transfer only between
purpose register and I/O port accumulator and I/O port
The memory map(64kb)is shared The I/O map is independent of the
between I/O device and system memory memory map,256 input device and 256
output device
More hardware is required to decode 16- Less hardware is required to decode 8-
bit address bit address
15. Define pipelining?
To speedup the execution of program, the instructions fetching and execution of instructions
are overlapped each other. This technique is known as pipelining. In pipelining, when then the
instruction is executed, the n+1 the instruction is fetched and thus the processing speed is
increased.
16. Discuss the function of instruction queue ?
3. 6-byte instruction queue is presented at the Bus Interface Unit (BIU). It is used to pre-fetch
and store at the maximum of 6 bytes of instruction code from the memory. Due to this,
overlapping instruction fetch with instruction execution increases the processing speed.
17.What are the basic units of microprocessosr?
. The basic units or blocks of a microprocessor are ALU, an array of registers

and control unit
18. Explain the process control instructions
STC – It sets the carry flag & does not affect any other flag
CLC – it resets the carry flag to zero &does not affect any other flag
CMC – It complements the carry flag & does not affect any other
flag
STD – It sets the direction flag to 1 so that SI and/or DI can be decremented automatically
after execution of string instruction & does not affect other flags
CLD – It resets the direction flag to 0 so that SI and/or DI can be incremented automatically
after execution of string instruction & does not affect other flags STI – Sets the interrupt flag
to 1. Enables INTR of 8086.
CLI – Resets the interrupt flagto0. 8086 will not respond to INTR.
19. What happens to the 8085 processor when it is reset?
When RESET IN pin is asserted low, the program counter, instruction register, interrupt mask bits
and all internal registers are cleared or reset. Also the RESET OUT signal is asserted high to clear
or reset all the peripheral devices in the system. After a reset, the content of program counter will
be 0000H and so the processor will start executing the program stored at 0000H.
20.In which lines the 8085 processor gives the output of IO port address during IO read/write
operation?
When the processor executes an IO read or write cycle, 8-bit port address is sent out both on low
order address bus and high order address bus. This facility offers a flexibility for system designer
to use either low-order address lines or high-order address lines for addressing ports and
generating chip select signals for IO devices.
21.When the 8085 processor checks for an interrupt?
In the second T-state of the last machine cycle of every instruction, the 8085 processor checks
whether an interrupt request is made or not.
22. What is interrupt acknowledge cycle?
The interrupt acknowledge cycle is a machine cycle executed by 8085 processor after acceptance
of the interrupt to get the address of the interrupt service routine in-order to service the interrupting
device.
23.What will be the status of the processor during bus idle cycle?
During bus idle cycle, the status signals S0 and S1 are both asserted low and data, address and
control pins are driven to high impedance state. Also, the processor will not sample the READY
signal.
24.How the slow peripherals are interfaced with 8085 processor?
The slow peripherals require longer read/write time than allowed by the processor. Hence to
interface slow peripherals, an extra hardware should be designed so that it introduces required
number of wait states in machine cycles between T1 and T2. An alternate solution is to interface
the slow peripherals using ports.
25.What is the difference between wait state and bus idle condition?
During bus idle condition, the tristate pins of the processor are driven to high impedance state, but
during wait state they are in normal states (either low or high). The READY is not sampled during
bus idle condition but it is sampled during wait state.
PART B
1.Draw and explain the architecture of 8085 in detail. (Nov/Dec-2013)
Address Bus:
The address bus is a group of 16 lines generally identified as A0 to A15. The address bus is
unidirectional and bits flow in one direction-from the MPU to peripheral devices.The MPU
uses the address bus to identify a peripheral or a memory (216 =
65,536) locations
Data Bus:
The data bus is a group of 8 lines used for data flow. These lines are bi-directional and data
flow in both directions between the MPU and memory and peripheral devices. The MPU
uses the data bus to transfer data.
Control Bus:
The control bus carries synchronization signals and providing timing signals.The MPU
generates specific control signals for every operation it performs.These signals are used to
identify a device type with which the MPU wants to communicate.
Registers of 8085:
The 8085 have six general-purpose registers to store 8-bit data dur ng program execution.
These registers are identified as B, C, D, E, H, and L.They can be combined as registerpairs-
BC, DE, and HL-to perform some 16-bit operations.
Accumulator (A):
The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).This
register is used to store 8-bit data and to perform arithmetic and logical operations.The result
of an operation is stored in the accumulator.
Flags:
The microprocessor uses the 5 flags for testing the data conditions.They are Zero (Z), Carry
(CY), Sign (S), Parity (P), a d Auxiliary Carry (AC) flags.The flagsare set or reset according
to the result of an operation.The bit position for the flags in flag register is,
Figure: Architecture of 8085 Microprocessor

1. Sign Flag (S): If D7 of the result is1, the sign flag is set. Otherwise it is
reset. D7 is reserved for indicating the sign;
If D7 is 1, the number will be viewed as negative number. If D7 is 0, the
number will be viewed as positive number.
2. Zero Flag (Z): If the result of arithmetic and logical operation is zero, then zero flag is
set. Other ise it is reset.
3. Auxiliary Carry Flag (AC): If D3 generates any carry when doing any arithmetic and
logical operation, this flag is set. Otherwise it is reset.
4. Parity Flag (P): If the result of arithmetic and logical operation contains even number of
1's then this flag will be set and if it is odd number of 1's it will be reset.
5. Carry Flag (CY):If any arithmetic and logical operation result any carry then carry
flag is set otherwise it is reset.
Arithmetic and Logic Unit (ALU):

It is used to perform the arithmetic operations like addition,subtraction, multiplication,
division, increment and decrement and logical operations like AND,OR and EX-OR.
It receives the data from accumulator and registers.According to the result the flag register
was set or reset.
Program Counter (PC):

This 16-bit register sequencing the execution of instructions. The function of the program
counter is to point to the memory address of the next instruction to be executed.When an
opcode is being fetched, the program counter is incremented by one to point to the next
memory location.
Stack Pointer (SP):

The stack pointer is also 16-bit register used as a memory pointer.It points to a memory location in
R/W m mory, called the stack.The beginning of the stack is defined by loading a 16-bit address in
the stack pointer.
Temporary Register:
It is used to hold the data during the arithmetic and logical operations.
Instruction Register:
When an instruction is fetched from the memory, it is loaded in the instruction register.
Instruction Decoder:
It gets the instruction from the instruction register and decodes the instruction. It
identifies the instruction to be performed.
Serial I/O Control:

It has two control signals named SID and SOD for serial data transmission.
Timing and Control unit :

It has three control signals ALE, RD (Active low) and WR (Active low) and three status
signals IO/M(Active low), S0 and S1.
ALE is used for provide control signal to synchronize the components of

microprocessor and timing for instruction to perform the operation.
RD (Active low) and WR (Active low) are used to indicate whether the operation is
reading the data from memory or writing the data nto memory respectively.
IO/M(Active low) is used to indicate whether the operation is belongs to the memory or
peripherals.
2.Draw the signal (pin diagram) configuration of 8085 and explain the purpose of
each signals. (Dec-2012)
8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows
 Power supply and clock signals
 Address bus
 Data bus
 Control and status signals
 Interrupts and externally initiated signals
 Serial I/O ports
 Direct Memory Access (DMA):
Fig:Pin Diagram of 8085 Microprocessor

Power supply and Clock frequency signals:
Vcc : + 5 volt power supply
Vss : Ground
X1, X2 : Crystal or R/C network or LC network connections to set the frequency of
internal clock generator.The frequency is internally divided by two. Since the basic
operating timing frequency is 3 MHz, a 6 MHz crystal is connected externally.
CLK (OUT):Clock Output is used as the system clock for peripheral and devices
interfaced with the microprocessor.
Address Bus:A8 - A15 (Input)

It carries the most significant 8 bits of the memory address or the 8 bits of the I/O
address;
Multiplexed Address / Data Bus:AD0 - AD7 (Input/Output)

These multiplexed set of lines used to carry the lower order 8 bit address as well as data
bus.
During the opcode fetch operation, in the first clock cycle, the lines deliver the
lower
order address A0 - A7.
In the subsequent IO / memory, read / write clock cycle the lines are used as
data bus.
TheCPU may read or write out data through these lines.
Control and Status signals:

Control Signals:
ALE (output) - Address Latch Enable.

This signal helps to capture the lower order address presented on the
multiplexed address / data bus.
RD (output , active low) - Read
This indicates that the selected memory location or I/O device is to be read and the data
bus is ready for accepting data from the memory or I/O device.
WR (output, active low) - Write

This indicates that the data on the data bus is to be written into the selected memory
location or I/O device.
IO/M (output) - Memory/ IO
This status signal indicates that the read / write operation relates to whether the memory or
I/O device.
It goes high to indicate an I/O operation.
It goes low for memory operations.
Status Signals:S1,S0
It is used to know the type of current operation of the microprocessor.
S1 S0 Operation Specified
0 0 Halt
0 1 Memory Or I/O Write
1 0 Memory Or I/O Read
1 1 Instruction Fetch
Interrupts and Externally initiated operations:

They are the signals initiated by an external device to request the microprocessor to do
a particular task or work.
There are five hardware interrupts called,
i) TRAP
ii) RST 7.5
iii) RST 6.5
iv) RST 5.5
v) INTR
TRAP interrupt is a nonmaskable restart interrupt. It is unaffected by any mask or

Interrupt Enable. It has the highest priority of any interrupt.
RESTART INTERRUPTS: These three inputs have the same timing as INTR. They
are RST 7.5,RST 6.5, RST 5.5
Types of Interrupts Priority
TRAP Highest
RST 7.5
RST 6.5
RST 5.5
INTR Lowest
On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low
INTA (Interrupt Acknowledge) signal.
Reset In (input, active low)

This signal is used to reset the microprocessor.
The program counter inside the microprocessor is set to zero.

The buses are tri-stated.
Fig:Signal Diagram of 8085 Miicroprocessor

Reset Out (Output)
It indicates CPU is being eset.

Used to reset all the connected devices when the microprocessor is reset.
Serial I/O ports:
SID (input) - Serial Input Data

Serial input data line The data on this line is loaded into accumulator bit 7 whenever
a RIM instruction is executed.
SOD (output) - Serial Output Data

The output SOD is set or reset as specified by the SIM instruction.
These signals are used for serial communication.
Direct Memory Access (DMA):
HOLD :HOLD signal is generated by the DMA controller circuit. The I/O device request the
processor for the address/data bus for bulk data transfer. HLDA:(HOLD
ACKNOWLEDGE) On receipt of HOLD signal, the microprocessor acknowledges the
request by sending out HLDA signal and leaves out the control of the buses. After the HLDA
signal the DMA controller starts the direct transfer of data.
READY (input)
Memory and I/O devices will have slower response compared to microprocessors.
Before completing the present job such a slow peripheral may not be able to handle further
data or control signal from CPU.
The processor sets the READY signal after completing the present job to access the data.
The microprocessor enters into WAIT state while the READY pin is disabled.
3.Explain the interrupt structure of 8085 microprocessor. (Nov/Dec-2013)
Interrupt is a signal s nd by an external device to the processor, to perform a

particular task or work. Mainly in the microprocessor based system the interrupts are used
for data transfer between the peripheral and the microprocessor. When a peripheral is ready
for data transfer, it interrupts the processor by sending an appropriate signal to the interrupt
pin of the processor. If the processor accepts the interrupt then the processor suspends its
current activity and executes an interrupt service subroutine to complete the data transfer
between the peripheral and processor. After executing the interrupt service routine the
processor resumes its current activity. This type of data transfer scheme is called interrupt
driven data transfer scheme.
Types of Interrupts :
The interrupts are classified into software interrupts and hardware interrupts.
SOFTWARE INTERRUPTS:
The software interrupts are program instructions. These instructions are inserted at desired
locations in a program. While running a program, lf a software interrupt instruction is
encountered, then the processor executes an interrupt service routine (ISR).
The software interrupts of 8085 are RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST6
and RST7.
All software interrupts of 8085 are vectored interrupts. The software interrupts cannot be
masked and they cannot be disabled. When the p ocessor encounters the software instruction,
it pushes the content of PC to stack. Th n loads the Vector address in PC and starts executing
the ISR stored in this vector address. At the end of ISR, a return instruction – RET will be
placed. When the RET instruction is executed, the processor POP the content of stack to PC.
Interrupt Vector address
RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H
HARDWARE INTERRUPTS:
The hardware interrupts are initiated by an external device by placing an appropriate signal at
the interrupt pin of the processor.The processor keeps on checking the interrupt pins at the
second T-state of last machine cycle of every instruction.If the processor finds a valid
interrupt signal and if the interrupt is unmasked and enabled, then the processor accepts the
interrupt.The acceptance of the interrupt is acknowledged by sending an INTA signal to the
interrupted device. The processor saves the content of PC in stack and then loads the vector
address of the interrupt in PC.If the interrupt is non-vectored, then the interrupting dev ce has
to supply the address of ISR
when it receives INTA signal. It starts executing ISR in this address.At the end of ISR, a
return instruction, RET will be placed.When the processor executes the RET instruction, it
POP the content of top of stack to PC. Thus the processor control returns to main program
after servicing interrupt.
The hardware interrupts of 8085 are TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR
Further the interrupts may be classified into VECTORED and NON-VECTORED
INTERRUPTS.
VECTORED INTERRUPT:
In vectored interrupts, the processor automatically branches to the specific address in
response to an interrupt.
The TRAP, RST 7.5, RST 6.5 and RST 5.5 are vectored interrupts.
The vector addresses of hardware interrupts are given in the table.
Interrupt Vector address
TRAP 0024H
RST 7.5 003CH
RST 6.5 0034H
RST 5.5 002CH
NON-VECTORED INTERRUPT:
In non-vectored interrupts the interrupted device should give the address of the interrupt
service routine (ISR).
The INTR is a non-vectored interrupt.
When a device interrupts through INTR, it has to supply the address of ISR after receiving
interrupt acknowledge signal.
TRIGGERING EDGE OF 8085 INTERRUPTS:
The TRAP interrupt is edge and level sensitive.To init ate TRAP, the interrupt signal has to
make a low to high transition and then it has to r main high until the interrupt is
recognized.The RST 7.5 interrupt is positive edge s nsitive. To initiate the RST 7.5, the
interrupt signal has to make a low to high tra sition and it need not remain high until it is
recognized.The RST 6.5, RST 5.5 and INTR are level sensitive interrupts.Hence for these
interrupts the interrupting signal should remain high, until it is recognized.
MASKABLE & NON-MASKABLE INETRRUPTS:

The hardware vectored interrupts a e classified into
Maskable Int rrupts.
Non-maskable Interrupts.
Non-maskable Interrupts:
The interrupts hich cannot be disabled are called Non-maskable Interrupts.
TRAP is non-maskable interrupt.
Maskable Interrupts:
The interrupts which can be enabled or disabled are called Maskable Interrupts.
RST 7.5, RST 6.5, RST 5.5 and INTR are Maskable interrupt.
Masking is preventing the interrupt from disturbing the main program.When an interrupt is
masked the processor will not accept the interrupt signal.The interrupts can be masked by
executing SIM instruction. (SIM - Set InterruptMask).The status of maskable interrupts can
be read into accumulator by executing RIM instruction (RIM - Read Interrupt Mask).All the
hardware interrupts, except TRAP are disabled, when the processor is resetted.They can also
be disabled by executing DI instruction. (Dl-Disable Interrupt).When an interrupt is disabled,
it will not be accepted by the processor.To enable the disabled interrupt, the processor has to
execute El instruction (El-Enable Interrupt).
INTERRUPT PRIORITY:
The order in which the interrupt has to be serviced is called Interrupt Priority.The priority
order of the 8085 interrupt is
Interrupt Interrupt Priority
TRAP 1
RST 7.5 2
RST 6.5 3
RST 5.5 4
INTR 5
4..Draw the timing diagram for Opcode Fetch machine cycle, Memory Read machine
cycle,MemoryWrite,I/O read machine cycle and I/O write machine Cycle. (Nov/Dec-
2014)
Instruction Cycle:
The time required to execute an instruction is called instruction cycle.
Machine Cycle
The time required to access the memory or input/output devices is called machine cycle.
T-State
A portion of an operation carried out in one system clock period is called as T-state.The
machine cycle and instruction cycle takes multiple clock periods.
Opcode Fetch Machine Cycle:

Opcode fetch cycle is part of any instruction execution. In this machine cycle 8085 fetches
opcode of instruction. The following are the sequence of actions that are performed by 8085
to fetch an opcode from memory. This machine cycle consists of 4 T-states.
8085 places 16-bit address from PC on to the address bus and issues ALE pulse in first T-
state (T1). This is used to de-multiplex the address and data bus. It also issues IO/M‟ signal
to „0‟. This indicates that processor is performing memory related operation. In second T-
state (T2) processor issues RD‟ control signal to memory. This enables memory to put data
present at the address location given in previous T-state on to data bus. RD‟ control signal is
active for two clock pulses.
Fig: Timing Diagram of 8085 Microprocessor
In T3 state memory places opcode on Data bus. Processor reads opcode present on data bus
and de-asserts RD‟ signal. Thus data bus goes into high impedance state.
In T4 state processor decodes instruction and necessary actions are performed.
Memory Read machine cycle:
This machine cycle is required when an operand is present in memory. This machine cycle
requires three T-states. The following are the sequence of actions performed by
microprocessor during this machine cycle.
In the first T-state (T1) 8085 places address on address bus and issues ALE signal.
And also IO/M‟ signal is made low, since it is memory related operation.
In the second T-state (T2), processor issues RD‟ control signal to memory. In response to
this memory places data on data bus.
In the third T-state (T3), processor reads data from data bus, and de-asserts RD‟ signal.
Memory Write Machine cycle:

This machine cycle is required when the results of operation needs to store in memory. This
machine cycle requires three T-states. The following are sequence of actions performed by
processor in this machine cycle.
In first T-state (T1), 8085 processor places 16- bit address on address bus and issues ALE
signal. And also it makes IO/M‟ signal to low, indicating it is memory related operation.
In second T-state (T2), processor places data to be written on data bus and asserts WR‟
signal to the memory.
In the third T-state (T3), memory stores the data and processor de-asserts WR‟ signal.
IO read machine cycle:

This machine cycle is required, when data needs to be read from an input device. This
machine cycle requires three T-states. The following are the sequence of actions performed
by processor during this machine cycle.
In the first T-state (T1) 8085 places port address(for IO mapped addresses port address is
8-bit, but for memory mapped addresses IO device address is 16-bit, but reading from such is
performed by memory read machine cycle) on address bus and issues ALE signal. And also
IO/M‟ signal is made high, since it is IO related operation.
In the second T-state (T2), processor issues RD‟ control signal to IO peripheral.
In response to this input device places data on data bus.
In the third T-state (T3), processor reads data from data bus, and de-asserts RD‟ signal.
IO write Machine cycle:
This machine cycle is required when data needs to be output to an output device. This
machine cycle requires three T-states. The following are the sequence of actions performed
by processor during this machine cycle.
In first T-state (T1), 8085 processor places 8-bit port address on address bus (for IO
mapped addresses port address is 8-bit, but for memory mapped addresses, IO device address
is 16-bit, but writing to such is performed by memory write machine cycle) and issues ALE
signal. And also it makes IO/M‟ signal to high, indicating it is IO related operation.
In second T-state (T2), processor places data to be written on data bus and asserts WR‟
signal to the peripheral.
In the third T-state (T3), peripheral accepts the data and processor de-asserts
WR‟ signal.
5.Explain how the memory organization was done in 8085.
8085 has 16 bit address bus, hence it can access 216 no. of memory locations,
which is equal to 64KB memory. Memory is required to store program as well as data.
Since microprocessor doesn‟t have on-chip memory, we need to connect it externally.So it
requires addressing mechanism.
The following are the steps involved in interfacing memory with 8085 processor.
1. First decide the size of memory requires to be nterfaced. Depending on this
we can say how many address lines are required for it. For example if you
2. want to interface 4KB (212) memory it requires 12 address lines. Remaining address
lines can be used in address decoding.
3. Depending on the size of memory r quired and given address range, construct address
decoding circuitry. This address decoding circuitry can be implemented with NAND gates
and/or decoders or using PAL.
4. Connect data bus of memory to processor data bus.
5. Generate the control signals required for memory using IO/M‟, WR‟, RD‟ signals of
8085 processor.
Example:
Interface 4KB memory to 8085 with starting address A000H.
1. 4KB memory requires 12 address lines for addressing as already mentioned. But 8085 has
16 address lines. Hence four of address lines are used for address decoding
2. Given that starting address for memory is A000H. So for 4KB memory ending address
becomes A000H+0FFFH (4KB) = AFFFH.
A0-A11 address lines are directly connected to address bus of memory chip. A12-A15 are
used for generating chip select signal for memory chip.
Address decoding circuit using 3X8 decoder:
A15 line is use for enabling 74x138 decoder chip. A12, A13, A14 lines are connected to
74X138 chip as inputs. When theses li es are 010 output should be „0‟. This is provided at
O2 pin of 74X138 chip.
Address decoding circuit using only NAND gates:
A15, A14, A13, A12 inputs should be 1010, for enabling the chip. So the circuit for this is
as shown above.
Types of address decoding:
There are two types of address decoding mechanism, based on address lines used for
generating chip select signal.
1. Absolute decoding
2. Partial decoding
Absolute decoding:
All the higher order lines of microprocessor, left after usi g the required signals for memory
are completely used for generating chip select s gnal.This type of decoding is called absolute
decoding.
Partial decoding:
Only some of the address lines of m croprocessor left after using the required signals
for memory are used for generating chip select signal. Because of this multiple address
ranges will be formed. If total memory space is not required for the system then, this type of
address decoding can be used. The advantage of this technique is fewer components are
required for memory interfacing because of this board size reduces and in turn cost reduces.
UNIT-II PROGRAMMING OF 8085 PROCESSOR
PART - A
1. What is indexing?NOV/DEC 2012
Indexing technique allows programmer to point or refer the data stored in sequential
memory locations one by one.
2.What are the various types of 8085 instructions? MAY/JUNE2013,NOV/DEC2011

1. Data transfer group – MOV A,B
2. Arithmetic group – ADD B
3. Logical group- ANA B
4. Branch group – JMP LABEL
5. Stack I/O and Machine Control group – PUSH,POP,HLT.
3. Explain the difference between a JMP instruction and CALL

instruction. MAY/JUNE2012
 A JMP instruction permanently changes the program counter.
 A CALL instruction leaves information on the stack so that the original
program execution sequence can be resumed.
4. What is meant by lookup table?NOV/DEC 2014

A lookup table is an array that replaces runtime computation with a simpler array
indexing operation.The savings in terms of processing time can be significant, since
retrieving a value from m mory is often faster than undergoing an expensive computation
or input/ouput operation.
5. Explain the functioning of CMP instructions?NOV/DEC 2015

This instruction subtracts the contents of the specified register from contents of
the accumulator and sets the condition flags as a result of the subtraction.
6. Mention the similarity and difference between compare and

subtract
instructions. May/June 2014
The compare and subtract instructions both are subtract one operand from
another and sets the flag register accordingly.The subtract instruction stores the result in
the accumulator while the compare instruction does not store any result except flags.
7. State the purpose and importance of NOP instruction. May/June 2014
The NOP instruction in CPU‟s is to insert a time delay.It may be useful to
force the CPU to wait for external (slower) devices to complete its work.
8. What are the different types of addressing modes?NOV/DEC

2013,MAY/JUNE 2012
The addressing modes specifies the location of the operand(data). The different
types are as follows
1. Immediate addressing
2. Register addressing
3. Direct addressing
4. Indirect addressing
5. Implicit addressing
9. Define stack and stack related instructions? MAY/JUNE 2013,NOV/DEC2012

The stack is a group of memory locat ons in the R/W memory that is used for the
temporary storage of binary information during the execution of the program. The stack
related instructions are PUSH and POP
10. State the function of given 8085 instructions:JP,JPE,JPO,JNZ

JP – Jump on positive S=0
JPE- Jump on parity even P=1
JPO- Jump on parity odd P=0
JNZ-Jump if no zero Z=0
11.What are subroutine?

Subroutine are group of instructions stored as a separate program in memory and
it is called from the main program whenever required.
12.What is a recursive procedures?

A recursive procedure is a procedure, which calls itself. Recursive procedures are
used to work with complex data structures called trees. If the procedure is called with
N=3,then the N is decremented by 1 after each procedure CALL and the procedure is
called until N=0.
13.How to access subroutine with in the main program procedure? NOV/DEC 2013
i) Accessed by CALL & RET instruction
ii)Machine code of instruction is put only once in the memory
iii)With procedures less memory is required
iv)Parameters can be passed in registers, memory location or stack
14.What are the four instructions which control the interrupt structure of the 8085
microprocessor?
DI(disable interrupts)
EI(enable interrupts)
RIM(read interrupt masks)
SIM(set interrupt masks)
15. How the microprocessor is synchronized with peripherals?

The timing and control unit synchron zes all the microprocessor operations with
clock and generates control signals necessary for communication between the
microprocessor and peripherals.
16. What is a recursive procedures?
A recursive procedure is a procedure,which calls itself.recursive procedures are

used to work with complex data structures called trees.if the procedure is called with
N=3,then the N is decremented by 1 after each procedure CALL and the procedure is
called until N=0.
17.How to access subroutine with in the main program procedure?

i) accessed by CALL & RET instruction
ii) machine code of instruction is put only once in the memory
with procedures less memory is required
iii) parameters can be passed in registers,memory location or stack
18. How the microprocessor is synchronized with peripherals?
The timing and control unit synchronizes all the microprocessor operations with
clock and generates control signals necessary for communication between the
microprocessor and peripherals.
19.What is DAA ?
DAA - Decimal Adjust Accumulator.

After BCD addition, this instruction is executed to get the result in BCD. When DAA
instruction is executed, the content of the accumulator is altered or adjusted as explained below
:
(i) If the sum of lower nibbles exceeds 09H or auxiliary carry is set, a correction 06H (0110) is
added to lower nibble.
(ii) If the sum of upper nibbles exceeds 09H or carry is set, a correction 06H (0110) is added to
upper nibble.
20.What is DAD and what are the flags affected by this instruction?
DAD refers to Double Addition. This instruction is used to perform addition of two 16-bit data.
Syntax : DAD rp
The content of register pair (rp) is added to the content of HL pair. After addition, the result
will be in HL pair. The register pair can be BC, DE, HL, or SP. On execution of this
instruction, only carry flag is affected.
21.List the various instructions that can be used to clear accumulator ?

The accumulator can be cleared by the following instructions:
1. MVI A,00H
2. SUB A
3. ANI 00H
4. XRA A.
22. What is the similarity and difference between subtract and compare instruction?
Similarity : Both the subtraction and comparison are performed by subtracting two data in ALU
and flags are altered depending upon the result.
Difference : After subtract instruction is executed, the result is stored in accumulator, but after
the execution of compare instruction the result is discarded ( i.e., the subtract instruction alters
the content of destination register (accumulator), but the compare instruction will not alter the
content of any register or memory).
23.List the assembler directives of a typical 8085 assembler.
23.How is a subroutine implemented in 8085?

A subroutine is written as a separate program (Procedure) and stored in a separate memory
location. The subroutine program should be terminated by an RET instruction. It is called in the
main program using CALL addr16 instruction. The addr16 should be the starting address of the
subroutine program.
When the CALL instruction is executed, the processor saves the return address (address of next
instruction) in stack, load the subroutine address in Program Counter(PC) and starts executing
the subroutine. At the end of subroutine when the RET instruction is executed, the return address
is
retrieved from the stack and loaded to the PC.
24.Write a simple delay subroutine involving a register pair of 8085.

25.Write a simple delay subroutine involving a single 8-bit register of 8085.
PART - B
1. What are the different addr ssing modes in 8085 microprocessor? Explain it
with an example? NOV/DEC 2015,NOV/DEC 2014,NOV/DEC 2012,MAY/JUNE
2012 MAY/JUNE 2011
Addressing mode specifies the location of operand(data).Every instruction of a

program has to operate on a data. The method of specifying the data to be operated by the
instruction is called Addressing.
The 8085 has the following 5 different types of addressing.
1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implied Addressing
1.Immediate Addressing :
In immediate addressing mode, the data is specified in the instruction itself. The data will
be a part of the program instruction.All instructions that have „I‟ in their mnemonics are
of Immediate addressing type.
Example: MVI A, 01H- Move the data 01H given in the instruction to A register.
2.Direct Addressing :
In direct addressing mode, the address of the data is specified in the instruction.The data
will be in memory. In this addressing mod , the program instructions and data can be
stored in different memory blocks. This type of addressing can be identified by 16-bit
address present in the instruction.
Example:LDA 4500H- Load the data available in memory location 4500H in A register.
3.Register Addressing :
In register addressing mod , the instruction specifies the name of the register in which the
data is available.This type of addressing can be identified by register names in the
instruction.
Example: MOV A, B -Move the content of B register to A register.
4.Register Indirect Addressing :

In register indirect addressing mode, the instruction specifies the name of the register in
which the address of the data is available. The data will be in memory and the address
will be in the register pair.
This type of addressing can be identified by letter „M‟ present in the instruction.
Example: MOV A, M - The content of memory (data) addressed by HL pair is

moved to A register.
5.Implied Addressing :
In implied addressing mode, the instruction itself specifies the type of operation and
location of data to be operated. This type of instruction does ot have any address, register
name, immediate data specified along with it.
Example:CMA - Complement the content of accumulator
2.Explain the Different types of instruction in 8085. NOV/DEC 2013,MAY/JUNE

2013,NOV/DEC 2012,MAY/JUNE 2012,MAY/JUNE 2011
An instruction is a command given to the m croprocessor to perform specified operation
on a given data.The instruction set of a microprocessor is the collection of instructions
that the microprocessor is designed to execute.It is classified into
1. Data Transfer Instructions.
2. A ithmetic Instructions.
3. Logical Instructions.
4. Branching / Control Transfer Instructions.
5. Stack & I/O Machine Control Instructions.
1.DATA TRANSFER INSTRUCTIONS:
The data transfer instructions move the data between registers or between registers and
memory. It copies the data from source location to destination location.No flags will be
affected.
MOVE INSTRUCTION:
MOV Rd, Rs
MOV M, Rs
MOV Rd, M
This instruction copies the contents of the source register into the destination register.
The contents of the source register are not altered.If one of the operands is a memory
location, its location is specified by the contents of the HL registers.
Example: MOV B, C - This instruction move the content of C register to B register.
MOV B, M -This instruction move the content of memory location pointed by HL
register to B register.
MOVE IMMEDIATE 8-BIT:
MVI Rd, data

MVI M, data
The 8-bit data is stored in the destination regist ror memory.If the operand is a memory
location, its location is specified by the contents of the HL registers.
Example:MVI A,01 - The data 01 will move to A register.
MVI M, 01 – The data 01 will move to the memory location pointed by HL

registers.
LOAD ACCUMULATOR:
LDA 16-bit address

The contents of a memory location, specified by a16-bit address in the operand, are
copied to the accumulator. The contents of the source are not altered. This is a 3-byte
instruction, the second byte specifies the low-order address and the third byte specifies
the high-order address.
Example: LDA 4000 –The content of memory location 4000 is loaded into A register.
STORE ACCUMULATOR:
STA 16-bit address
The contents of the accumulator are copied into the memory location specified by the
operand.This is a 3-byte instruction, the second byte specifies the low-order address and
the third byte specifies the high-order address.
Example: STA 4500–The content of A register is loaded into memory location 4500.
EXCHANGE:
XCHG
The contents of register H are exchanged with the contents of register D, and the contents
of register L are exchanged with the contents of re ister E.
Example: XCHG :This instruction exchange the content of H and L with D and E
2.ARITHMETIC INSTRUCTIONS:
The arithmetic instructions includes addition, subtraction ,increment and decrement
operations.
ADDITION:
ADD REGISTER OR MEMORY TO ACCUMULATOR
ADD Rs
ADD M
The contents of the operand (register or memory) are added to the contents of the
accumulator and the result is stored in the accumulator. If the operand is a memory
location, its location is specified by the contents of the HL registers. All flags are
modified to reflect the result of the addition.
Example: ADD B – The content of A register is added with the content of B register and
the result is stored in A register.
ADD M -The content of A register is added with the content of
memory location pointed by HL register and the result is stored in A register.
ADD REGISTER TO ACCUMULATOR WITH CARRY:

ADC R
ADC M
The contents of the operand (register or memory) and the Carry flag are added to the
contents of the accumulator and the result is stored in the accumulator.If the operand is a
memory location, its location is specified by the contents of the HLregisters. All flags are
modified to reflect the result of the addition.
Example: ADC B -The content of A register is added with the content of B register and
also Carry and the result is stored in A register.
ADC M - The content of A register is added with the content of memory location
pointed by HL register and also carry and the result is stored in A register.
ADD IMMEDIATE TO ACCUMULATOR
ADI 8-bit data

The 8-bit data (operand) is added to the contents of the accumulator and the result is
stored in the accumulator.All flags are modified to reflect the result of the addition.
Example: ADI 45 – The data 45H is immediately added with the content of A
register and result Is stored in A register.
SUBTRACTION:
SUBTRACT REGISTER OR MEMORY FROM ACCUMULATOR

SUBRs
SUB M
The contents of the operand (register or memory) are subtracted from the contents of the
accumulator and the result is stored in the accumulator.If the operand is a memory
location, its location is specified by the contents of the HLregisters.All flags are modified
to reflect the result of the subtraction.
Example: SUB B – The content of A register is subtracted with the content of B register
and the result is stored in A register.
SUB M -The content of A register is subtracted with the content of memory

location pointed by HL register and the result is stored in A register.
SUBTRACT SOURCE AND BORROW FROM ACCUMULATOR :
SBB R
SBB M
The contents of the operand (register or memory ) and the Borrow flag are subtracted
from the contents of the accumulator and the result is placed n the accumulator. If the
operand is a memory location, its location is specified by the contents of the HL
registers.All flags are modified to reflect the result in accumulator.
Example: SBB B -The content of A register is subt acted with the content of B register
and also Borrow flag and the result is stored in A r gist r.
SBB M - The content of A register is subtracted with the content of memory
location pointed by HL register and also Borrow and the result is stored in A register.
SUBTRACT IMMEDIATE FROM ACCUMULATOR:

SUI 8-bit data
The 8-bit data (operand) is subt acted from the contents of the accumulator and the result
is stored in the accumul tor. All flags are modified to reflect the result of the subtraction.
Example: SUI 45 -The data 45H is immediately subtracted with the content of A register
and Result is stored in A register.
INCREMENT REGISTER OR MEMORY

INR R
INR M
The contents of the designated (register or memory) are incremented by 1 and the result
is stored in the same place.If the operand is a memory location, its location is specified
by the contents of the HL registers.
Example:INR B – The content of B register is incremented by 1.
INR M – The content of memory location pointed by HL register is incremented by 1.

INCREMENT REGISTER PAIR:
INX R
The contents of the designated register pair are incremented by1 and the result is stored in
the same place.
Example: INX H – The HL register pair is incremented by 1 a d showing the next
memory location.
DECREMENT REGISTER OR MEMORY

DCR R
DCR M
The contents of the designated (register or m mory) are decremented by 1 and the result
is stored in the same place.If the operand is a memory location, its location is specified
by the contents of the HL registers.
Example:DCR B – The content of B register is decremented by 1.
DCR M –The content of memory location pointed by HL register is decremented by 1.
DECREMENT REGISTER PAIR:

DCX R
The contents of the designated register pair are decremented by1 and the result is stored
in the same place.
Example: DCX H – The HL register pair is decremented by 1 and showing the previous
Memory location.
3.LOGICALINSTRUCTIONS:
The logical instructions includes AND,OR,XOR,Complement operations.
Logical AND :
Logical AND register or memory with accumulator
ANA R
ANA M
The contents of the accumulator are logically ANDed with the contents of the operand
(register or memory), and the result is placed in the accumulator.If the operand is a
memory location, its address is specified by the contents of HL registers.S, Z, P are
modified to reflect the result of the operation. CY is reset. AC s set.
Example: ANA B - The content of A register is ANDed with the content of B register
ANA M - The content of A register is ANDed with the content of
memory location pointed by HL register and the result is stor d A register.
LOGICAL AND IMMEDIATE WITH ACCUMULATOR

ANI 8-bit data
The contents of the accumulator are logically ANDed with the 8-bit data (operand) and
the result is placed in the accumulator.S, Z, P are modified to reflect the result of the
operation. CY is reset. AC is set.
Example: ANI 45 -The data 45H is immediately ANDed with the content of A register
and result is stored in A register.
EXCLUSIVE OR REGISTER OR MEMORY WITH ACCUMULATOR
XRA R
XRA M
The contents of the accumulator are Exclusive ORed with the contents of the operand
(register or memory), and the result is placed in the accumulator.If the operand is a
memory location, its address is specified by the contents of HL registers.
S, Z, P are modified to reflect the result of the operation. CY and AC are reset.
Example: XRA B -The content of A register is XORed with the content of B register
XRA M -The content of A register is XORed with the content of
memory location pointed by HL register and the result is stored A
register.
EXCLUSIVE OR IMMEDIATE WITH ACCUMULATOR

XRI 8-bit data
The contents of the accumulator are Exclusive ORed with the8-bit data (operand) and the
result is placed in the accumulator.S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: XRI 45 -The data 45H is immediately XOR d with the content of A register
LOGICAL OR REGISTER OR MEMORY WITH ACCUMULATOR
ORA R
ORA M
The contents of the accumul tor are logically ORed with the contents of the operand
(register/memory), and the R sult is placed in the accumulator.If the operand is a memory
location, its address is specified by the contents of HL registers.
S, Z, P are modified to reflect the result of the operation. CY and AC are reset.
Example: ORA B -The content of A register is ORed with the content of B register
ORA M- The content of A register is ORed with the content of
memory location pointed by HL register and the result is stored A register.
LOGICAL OR IMMEDIATE WITH ACCUMULATOR:

ORI 8-bit data
The contents of the accumulator are logically ORed with the8-bit data (operand) and the
result is placed in the accumulator.S, Z, P are modified to reflect the result of the
operation. CY and AC are reset.
Example: ORI 45 - The data 45H is immediately ORed with the content of A register
COMPLEMENT ACCUMULATOR:
CMA
The contents of the accumulator are complemented.
No flags are affected.
Example: CMA
COMPLEMENT CARRY:
CMC
The Carry flag is complemented.No other flags are affected.
Example: CMC
SET CARRY :
STC
The Carry flag is set to 1.No other flags are affected.
Example: STC
4. BRANCHING (CONTROL TRANSFER)INSTRUCTIONS :
The branching instructions are used to change the execution order.They are divided into
conditional jump/call or unconditional jump/call.
JUMP UNCONDITIONALLY
JMP 16-bit address

The program sequence is transferred to the memory location specified by the 16-bit
address given in the operand.
Example: JMP 4000
JUMP CONDITIONALLY
The program sequence is transferred to the memory location spec f ed by the 16- bit
address given in the operand based on the specified flag of the PSW.
Example:
OPCODE DESCRIPTION FLAG STATUS

JC Jump on Carry CY=1
JNC Jump on no Carry CY=0
JP Jump on Positive S=0
JM Jump on Minus S=1
JZ Jump on Zero Z =1
JNZ Jump on no Zero Z=0
JPE Jump on parity even P=1
JPO Jump on parity odd P=0
UNCONDITIONAL SUBROUTINE CALL :
CALL 16-bit address

address given in the operand. Before the transfer, the address of the next instruction after
CALL the contents of the program counter is pushed onto the stack.
Example: CALL 4000
CONDITIONAL SUBROUTINE CALL :

address given in the operand based on specified flag of the PSW. Before the transfer, the
address of the next instruction after the call the contents of the program counter is pushed
onto the stack.
Example: CZ 4000

CC Call on Carry CY=1
CNC Call on no Carry CY=0
CP Call on Positive S=0
CM Call on Minus S=1
CZ Call on Zero Z =1
CNZ Call on no Zero Z=0
CPE Call on parity even P=1
CPO Call on parity odd P=0
UNCONDITIONALRETURN FROM SUBROUTINE:
RET
The program sequence is transferred from the subroutine to the calling program. The two
bytes from the top of the stackare copied into the program counter, and program
execution begins at the new address.
Example: RET
CONDITIONAL RETURN FROM SUBROUTINE:

The program sequence is transferred from the subroutine to the calling program based on
the specified flag of the PSW.The two bytes from the top of the stack are copied into the
program counter, and program execution begins at the new address.
Example: RZ
RC Return on Carry CY=1
RNC Return on no Carry CY=0
RP Return on Positive S=0
RM Return on Minus S=1
RZ Return on Zero Z =1
RNZ Return on no Zero Z=0
RPE Return on parity even P=1
RPO Return on parity odd P=0
5.STACK I/O,MACHINE CONTROL INSTRUCTIONS:
These instructions are used to manipulate the stack to perform the input /output and to
alter the internal control flags.Unless specified the flags are not affected.
STACK INSTRUCTION:
PUSH :
Example: PUSH PSW
The contents of register A and the contents of condition flags which form the PSW are
pushed onto the stack.
POP INSTRUCTION:
Example: POP PSW
The contents of register A and the contents of condition flags which form the PSW are
restored from the stack
I/O INSTRUCTION :
IN port
The data placed on the 8 bit bidirectional data bus by the specified port is moved to
register A.
OUT port
The contents of register A are placed on the 8 bit data bus is transferred to the specified
port.
MACHINE CONTROL INSTRUCTION:

EI
The interrupt system is enabled.
DI
The interrupt system is disabled.
NOP
No Operation is performed.No flags are affected.
HLT
The processor is stopped.No flags are affected.
3.Write an 8085 ALP to add, subtract, multiply and divide two 8 bit
numbers stored at consecutive memory locations. NOV/DEC 2015
8 BIT ADDITION:
ALGORITHM:
1. Initialize memory pointer to data location.

2. Get the first number from memory in accumulator.
3. Get the second number and add it to the accumulator.
4. Store the answer at another memory location.
PROGRAM:
8 BIT SUBTRACTION:

2. Get the first number from memory in accumulator.
3. Get the second number and subtract from the accumulator.
ALGORITHM:
LOGIC: Multiplication can be done by repeated addition.

2. Move multiplicand to a register.
3. Move the multiplier to another register.
4. Clear the accumulator.
5. Add multiplicand to accumulator
6. Decrement multiplier
7. Repeat step 5 till multiplier comes to zero.
8. The result, which is in the accumulator, is sto ed in a memory location.
PROGRAM:
8 BIT DIVISION:
ALGORITHM:
LOGIC: Division is done using the method Repeated subtraction.

1. Load Divisor and Dividend
2. Subtract divisor from dividend
3. Count the number of times of subtraction which equals the quotient
4. Stop subtraction when the dividend is less than the divisor The
dividend now becomes the remainder. Otherwise go to step 2.
5. stop the program execution.
PROGRAM:
4.Write an 8085 ALP to find largest & smallest numbers. MAY/JUNE 2011
LARGEST NUMBER:
ALGORITHM:
1. Place all the elements of an array in the consecutive memory locations.

2. Fetch the first element from the memory location and load it in the
accumulator.
3. Initialize a counter (register) with the total number of elements in an array.

4. Decrement the counter by 1.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next
element).
7. If the accumulator content is smaller, then move the memory
content (largest element) to the accumulator. Else continue.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.
PROGRAM:
SMALLEST NUMBER:
ALGORITHM:
1. Place all the elements of an array in the consecutive memory locations.

2. Fetch the first element from the memory location and load it in the
accumulator.
3. Initialize a counter (register) with the total number of elements in an array.
5. Increment the memory pointer to point to the next element.
6. Compare the accumulator content with the memory content (next
element).
7. If the accumulator content is smaller, then move the memory
content (largest element) to the accumulator. Else continue.
9. Repeat steps 5 to 8 until the counter reaches zero
10. Store the result (accumulator content) in the specified memory location.
PROGRAM:
5.Write an 8085 ALP to arrange in ascending and descending order.
MAY/JUNE 2013,MAY/JUNE 2012
Ascending Order:
ALGORITHM:
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbe s a d if the first number is larger than
second then interchange the number.
3. If the first number is small r, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order
PROGRAM:
DESCENDING ORDER
ALGORITHM:
1. Get the numbers to be sorted from the memory locations.
2. Compare the first two numbers and if the first numb r is
smaller than second then interchange the number.
3. If the first number is larger, go to step 4
4. Repeat steps 2 and 3 until the numbers are in required order
PROGRAM:
UNIT-III
8051 MICROCONTROLLER
PART - A
1. What is Microcontroller?
A device which contains the microprocessor with integrated peripherals like memory, serial ports,
parallel ports, timer/counter, interrupt controller, data acquisition interfaces like ADC, DAC is called
microcontroller.
2. List the features of 8051 microcontroller. (Nov/Dec 2014)

The features are single supply +5 volt operation using HMOS tech ology. 4096 bytes program
memory on chip (not on 8031), 128 data memory on ch p, Four register banks, Two multiple modes,
16-bit timer/counter, Extensive Boolean processing capabilities, 64 KB external RAM size
3. How is the Program memory organized in an 8051 Microcontroller?

In an 8051 based system the entire 64KB program m mory can be external or 4 KB is internal and the
remaining 60 KB is external. This is decided by the logic level of the signal EA Pin. When EA pin is
tied high (+Vcc or 5 V) the first 4 KB of program memory is internal and the remaining 60 KB is
exter al. When EA pin is tied low (GND or 0 V) the internal ROM is ignored and the entire 64 KB is
external.
4. List the alternative functions assigned to port 3 pins of 8051 microcontroller. (May/June
2011)
Port 3 3Alternative
pins function
P3.0 Received Data
P3.1 Transmission Data
P3.2 INT0
P3.3 INT1
P3.4 T0
P3.5 T1
P3.6 WR
P3.7 RD
5. What is the role of DPTR in 8051 Microcontroller?
The Data Pointer (DPTR) is the 8051s only user-accessible 16-bit (2-byte) register. The
Accumulator, "R" registers, and "B" register are all 1-byte values. DPTR, as the name suggests, is
used to point to data. It is used by a number of commands which allow the 8051 to access external
memory. When the 8051 accesses external memory it will access the external memory at the address
indicated by DPTR. While DPTR is most often used to point to data in external memory, many
programmers often take advantage of the fact that it‟s the only true 16-bit register available. It is
often used to store 2-byte values which have nothing to do with memory locations.
6.What is stack pointer (sp)? (EE2354 April/May2011)
Stack pointer (SP) is a 8 bit wide register and is incremented before the data is stored into the stack
using PUSH or CALL instructions. It contains 8-bit stack top address. It is defined anywhere in the
on-chip 128-byte RAM. After reset, the SP register is initialized to 07. After each write to stack
operation, the 8-bit contents of the operand are stored onto the stack, after incrementing the SP
register by one. It is not a top-down data structure. It is allotted an address in the special function
register bank.
7. Give the purpose of ALE/PROG signal. (May/June2014)
ALE/PROG is an address latch enable output pulse and indicates that valid address bits available on
the respective pins. The ALE pulses are emitted at a rate of one-sixth of the oscillator frequency. The
signal is valid only for external memory accesses.
8. Write the vector address and priority sequence of 8051 interrupts (Nov/Dec 2014)
The interrupts are Vector address
:
External interrupt 0 IE0: 0003H
:
Timer interrupt 0 TF0:000BH
:
External interrupt 1 IE1: 0013H
:
Timer Interrupt 1 TF1:001BH
:
Serial interrupt RI: 0023H
:
Transmit interrupt TI: 0023H
:
9. What are the addressing modes of 8051 microcontroller? (Nov/Dec 2014) The 8051 provides a
total of five distinct addressing modes.
(1) Immediate
(2) register
(3) direct
(4) register indirect
(5) indexed
10. Mention the purpose of PSEN and EA in 8051microcontroller. (May/June 2014)

PSEN: If external ROM is used for storing program then a logic zero (0) appears on it every time the
microcontroller reads a byte from memory.
EA : By applying logic zero to this pin, P2 and P3 are used for data and address transmission with no
regard to whether there is internal memory or not. It means that even there is a program written to the
microcontroller, it will not be executed. Instead, the program written to external ROM will be
executed. By applyi g logic one to the EA pin, the microcontroller will use both memories, first
internal then external (if exists).
11. List the interrupt sources in 8051 microcontroller. (May/June 2014) (Nov/Dec 2015)
8051 Microcontroller has 5 interrupts:

(1) External interrupt 0
(2) External interrupt 1
(3) Timer0 overflow
(4) Timer1 overflow
(5) Transmission interrupt (TI)/ reception interrupt (RI)
(6) ) Reset.
12. What is the function of R registers in 8051 Microcontroller? (May/June 2013)

The R registers are in a group of register banks denoted as bank 0 to bank 3. The R registers of any
bank can take value from 0 to 7. At any one time the controller can use any one of the register banks
as general purpose registers. The selection of register banks depends on the value of the bits RS0 and
RS1 in the PSW registers. After a reset the PSW register is cleared nd so the controller works with
register bank0.
13. Give the details of PSW of 8051. (May/June 2010)

The PSW stores the status of the results of the ALU operations and some of the status of the
processor by means of 1 bit status flags. The PSW is also known as flag register. The flags are useful
for the programmer to test condition of the result and make decisions. The PSW consists of four math
flags and two register bank select bits. The Math flag are carry, auxiliary carry, overflow and parity
flag. The register bank select bits are RS0 and RS1.
14.Differentiate between program memory and data memory. Program Memory
i) It stores the programs to be executed.

ii) It stores only program code which is to be executed and thus it need not be written, so it is
implemented using EPROM It stores the data, line intermediate results, variables and constants
required for the execution of the program.
Data Memory:The data memory may be read from or written to and thus it is implemented using RAM.
15. Explain relative addressing in an 8051.

In relative addressing, the instruction specifies the address relative to the PC(Program Counter). The
instruction will carry an offset whose range is -12810 to +12710. The offset is added to the PC to generate
the 16 bit physical address.
Example: JC offset- If carry is one, then the program control jumps to an address obtained by adding the
content of the PC and the offset value in the instruction.
16. List the instructions that affect the overflow flag in 8051
ADD,
ADDC,
SUBB,
DIV and
MUL.
17. Write the functions of TMOD register in 8051 Microcontroller. (Nov/Dec 2015)
18.Write a program to save the status of bits p1.2 and p1.3 on ram bit locations 6 and 7
respectively.
MOV C, P1.2; save status of P1.2 on CY

MOV O6, C; save carry in RAM bit location 06
MOV C, p1.3; save status of p1.3 on CY
MOV 07, C; save carry in RAM bit location 07.
19. Write a program to see if bits 0 and 5 of register b r1. If they are not, make them so
and save it in r0. (Nov/Dec2011)
JNB OFOH, NEXT – 1; JUMP if B.0 is low

SET BOFOH; Make bit B.0 high
NEXT – 1:JNB OF5H, NEXT – 2; JUMP if B.5 is low
SETB OF5H; Make B.5 high
NEXT – 2: MOV R0, B; Save register B.
20.. Compare Microprocessor and Microcontroller. (Nov/Dec 2006,2011)
Sl.No Microprocessor Microcontroller
Microprocessor contains ALU,

general purpose registers, stack Microcontroller contains the
pointer, program counter, clock circuitry of microprocessor and in
timing circuit and interrupt addition it has built in ROM, RAM,
1 circuit. I/O devices, timers and counters.
It has many instructions to It has one or two instructions to

move data between memory and move data between memory and
2 CPU. CPU.
It has one or two bit handling

It has many bit handling instructions.
3 instructions.
Access times for memory and Less access time for built-in memory
4 I/O devices are more and I/O devices
Microcontroller Based system

Microprocessor based system
requires less hardware reducing PCB
requires more hardware
5 size and increasing the reliability.
21. What are the special function register? (EE2354 April/May2012)
The special function register are stack pointer, index pointer (DPL and DPH), I/O port addresses, status
(PSW) and accumulator.
22. What are the uses of accumulator register?
The accumulator registers (A and B at addresses OEOh and OFOh, respectively) are used to store
temporary values and the results of arithmetic operations.
23. What is PSW? (EE2354 Nov/Dec2011)
Program status word (PSW) is the set of flags that contains the status information and is considered as
one of the special function register.
Give the purpose of ALE/PROG signal. (May/June2014)
ALE/PROG is an address latch enable output pulse and indicates that valid address bits available on the
respective pins. The ALE pulses are emitted at a rate of one-sixth of the oscillator frequency. The signal is valid
only for external memory accesses.
24.Explain the two power saving mode of operation. (April/May2011)
The two power saving modes of operation are:
Idle mode: In this mode, the oscillator continues to run and the interrupt, serial port and timer blocks are
active, but the clock to the CPU is disabled. The CPU status is preserved. This mode can be terminated
with a hardware interrupt or hardware reset signal. After this, the CPU resumes program execution from
where it left off.

Power down mode: In this mode, the on-chip oscillator is stopped. All the functions of the controller
are held maintaining the contents of RAM. The only way to terminate this mode is hardware reset. The
reset redefines all the SFRs but the RAM contents are left unchanged.

25.What are the two main features of sfr addresses?
The following two points should be noted SFR addresses.
The special function registers have addresses between 80H and FFH. These addresses are above 80H,
since the addresses 00 to 7FH are addresses of RAM memory inside the 8051.

Not all the address space of 80 to FH is used by the SFR. The unused locations 80Hto FFH are
reserved and must not used by the 8051 programmer.

PART - B
1. Explain with a neat block diagram the architectu e of 8051microcontroller.
(May/June 2013) (May/June 2015)
The 8051 microcontroller is an 8-bit m crocontroller.The major components of

8051microcontroller and their functions
1.ALU(ArithmeticandLogicUnit)
2.PC(ProgramCounter)
3.Registers
4.Timersandcounters
5.InternalRAMandROM
6.Fourparallelinput/outputports
7.Interruptcontrollogic ithfivesourcesofinterrupt
8.Serialdatacommunication
9.PSW(ProgramStatusWord)
10.DataPointer(DPTR)
11StackPointer(SP)
12.Address and Data bus.
13.Clock Circuits.
Fig:Architecture of 8051 Microcontroller
1. Arithmetic and Logic Unit (ALU):

All arithmetic and logical functions are carried out by the ALU.
Addition, subtraction with carry, and multiplication come under arithmetic operations.
Logical AND, OR and EXOR come under logical operations.
2.ProgramCounter(PC):
A program counter is a 16-bit register and it has no internal address.The basic function of program
counter is to fetch the next instruction to be executed.The PC increments automatically, holding the
address of the next instruction.
3.Registers:
Registers are usually known as data storage devices. 8051 microcontroller has 2 registers, namely
Register A and Register B.These registers are used to store the output of mathematical and logical
instructions.
Accumulator(A Register):
A Register serves as an accumulator.The operat ons of addition, subtraction,

multiplication and division are carried out by A R gist r A Register is also involved in
data transfers between the microcontroller and xt rnal memory.
B Register:
Register B functions as a general purpose register. Register B is usually unused and comes into
picture only when multiplication and division functions are carried out by Register A.
4. Timers and Counters :

Microcontroller 8051 has TWO 16 bit timers and counters.
The two timers are Timer0 and Timer1.
The two timers are divided into TH0 (8bit)TL0(8bit) and TH1(8bit)TL1(8bit).
5. Internal RAM and ROM:

ROM
The 8051 has a memory of 4KB on-chip ROM.
The 8051 ROM is a non-volatile memory.
It is also called as program memory.
RAM
The 8051 microcontroller is composed of 128 bytes of internal RAM. This is a volatile memory
since its contents will be lost if power is switched off. These 128 bytes of internal RAM are divided
into 32 working registers.This 32 working registers divided into 4 register banks (Bank 0-Bank 3)
with each bank consisting of 8 registers (R0 - R7). There are 128 addressable bits in the internal
RAM.It is also called as program memory.
6.FourParallelInput/OutputPorts:
The 8051 microcontroller has four 8-bit input/output ports. These are: P0,P1,P2,P3.
PORT P0:
When there is no external memory present, this port acts as a general purpose input/output port.In
the presence of external memory, it functions as a multiplexed address and data bus. It performs
dual funct ons.
PORT P1:
This port is used for various interfacing activities.This 8-bit port is a normal I/O port.
PORT P2:
This port can be used as a g n ral purpose port when there is no external memory.
When external memory is present it works in conjunction with PORT PO as an address
bus.
.
PORT P3:
PORT P3 behaves as a dedicated I/O port.
.InterruptControl:
A signal which is used to suspend or halt the normal program execution for a temporary period of
time in order to serve the request of another program or hardware device is called an interrupt. An
interrupt can either be an internal or external.
There are two ways of giving interrupts to a microcontroller
sending software instructions
sending hardware signals.
The interrupt mechanism keeps the normal program execution in a "put on hold" mode and
executes a subroutine program and after the subroutine is executed, it gets back to its normal
program execution.
In8051,5sourcesofinterruptsareprovided.Theyare:
a)2ExternalinterruptsourcesINT0andINT1
b) 3 Internal interrupt sources - Serial port interrupt, Timer Flag 0 and Timer Flag 1.
8. Serial Data Communication :
A method of establishing communication among computers is by transmitting and receiving data

bits is a serial con ection network.The SBUF(Serial Buffer) register holds the data.The SBUF
register h s 2 parts – one for storing the data to be transmitted (done using TXD pin) and another for
receiving data (done using RXD pin)from outer sources.
The SCON (Serial Control) register manages the data communication.The PCON (Power Control)
register manages the data transfer rates.Two pins - RXD and TXD, establish the serial
network.There are 4 programmable modes in serial data
communication.
They are:
1.SerialDatamode0(shiftregistermode)
2.SerialDatamode1(standardUART)
3.SerialDatamode2(multiprocessormode)
4. Serial Data mode 3
9.PSW(ProgramStatusWord):
Program Status Word is a register which holds a program's information and also monitors
the status of the program currently being executed.
PSW also has a pointer which points towards the address of the next instruction to be executed.
10.DataPointer(DPTR):
The data pointer or DPTR is 16-bit register. It is made up of two 8-bit registers called
DPH and DPL. Separate addresses are assigned to each of DPH and DPL. These 8-
bit registers are used for the storing the memory address.
11.StackPointer(SP):
The stack pointer (SP) in 8051 is an 8-bit register. The main purpose of SP is to
access the stack. Stack is a special area of data in memory. The SP acts as a pointer
for an address that points to the top of the stack.
12.DataandAddressBus:
A bus is group of wires using which data transfer takes place from one location to another
within a system There are mainly two kinds of buses - Data Bus and Address Bus
Data Bus:
The purpose of data bus is to transfer data. The no of data lines decides the word
length of the microcontroller. The data bus is bidirectional.
Address Bus:
The purpose of address bus is to transfer information. The information tells from
where within the components, the data should be sent to or received from. The no of
address lines decides the capacity of memory address. The address bus is
unidirectional.
13.Clock Circuits:
Internal operations can be synchronized using clock circuits which produce clock
pulses.
With each clock pulse, a particular function w ll be done and hence synchronization
is achieved. There are two pins XTAL1 and XTAL2 which form an oscillator circuit
which connect to a resonant network in the microcontroller.Quartz crystal is used to
generate gate pulse.
1. ALE(Address Latch Enable)Latches the address signals on Port P0
2. EA (External Address) - Holds the 4K bytes of program memory
3. PSEN (Program Store Enable) - Reads external program memory
4. RST (Reset) - Reset the ports and internal registers upon start up
2. Explain the interrupt structure of 8051 microcontroller. (May/June 2015)
An interrupt is a signal which interrupts normal program execution.
Program flow is always sequential, being altered only by those instructions and cause
program flow to deviate. Interrupts give to "put on hold" the normal program flow,
and execute a subroutine. After completion of subroutine microcontroller resume
normal program flow. This subroutine, called an ISR, which is only executed when a
certain interrupt occurs. The microcontroller 8051 has the following interrupt signals
External 0 Interrupt
Timer 0 over flow Interrupt
Timer 1 over flow Interrupt
Serial Interrupt
The various interrupts and their different code depending on interrupt was executed.
This is done by jumping to a fixed address when a given interrupt occurs.
Types of Interrupts Interrupt Flag Interrupt Address
External 0 Interrupt IE0 0003H
Timer 0 over flow Interrupt TF0 000BH
External 1 Interrupt IE1 0013H
Timer 1 over flow Interrupt TF1 001BH
Serial Interrupt RI/TI 0023H
Whenever Timer 0 overflows (i.e., the TF0 bit is set), the main program will be
temporarily suspended and control will jump to 000BH.The program code at address
000BH that handles the interrupt of Timer 0 overflowing.
Interrupt Enable Register (IE Register):

Polling Sequence:
The 8051 automatically evaluates whether an interrupt should occur after every
instruction. When checking for interrupt conditions, it checks them in the following
order:
Timer 0 Interrupt
Timer 1 Interrupt
Serial Interrupt
This means that if a Serial Interrupt occurs at the exact same instant that an External
0 Interrupt occurs, the External 0 Interrupt will be executed first and the Serial
Interrupt will be executed once the External 0 I terrupt has completed.
Interrupt Priorities :
The 8051 offers two levels of interrupt priority: high and low. By using interrupt
priorities you may assign higher priority to certain interrupt conditions.Interrupt
priorities are controlled by the IP SFR (B8h).
Interrupt Priority Register (IP Register):

D7 D6 D5 D4 D3 D2 D1 D0
* * * PS PT1 PX1 PT0 PX0

The rules for interrupt priorities:
 Nothing can interrupt a high-priority interrupt--not even another high priority

interrupt.
 A high-priority interrupt may interrupt a low-priority interrupt.
 A low-priority interrupt may only occur if no other interrupt is already executing.
If two interrupts occur at the same time, the interrupt with higher priority will
execute first. If both interrupts are of the same priority the interrupt which is
serviced first by polling sequence will be executed first.
Interrupt Signal Performance:
When an interrupt is triggered, the following actions are taken automatically by the
microcontroller
 The current Program Counter is saved on the stack, low-byte first.

 Interrupts of the same and lower priority are blocked.
 In the case of Timer and External interrupts, the corresponding interrupt
flag is cleared.
 Program execution transfers to the corresponding interrupt handler
vector address.
The Interrupt Handler Routi ne executes.
If the interrupt being handled is a Timer or External interrupt, the microcontroller

automatically clears the interrupt flag before passing control to your interrupt handler
routine.
End of Interrupt:
An interrupt ends when the program executes the RETI (Return from Interrupt)
instruction. When the RETI instruction is executed the following actions are taken by
the microcontroller:
 Two bytes are popped off the stack into the Program Counter to restore normal
program execution.
 Interrupt status is restored to its pre-interrupt status.
Serial Interrupts :
Serial Interrupts are slightly different than the rest of the interrupts. There are two
interrupt flags: RI and TI. If either flag is set, a serial interrupt is triggered. In the
serial port, the RI bit is set when a byte is received by the serial port and the TI bit is
set when a byte has been sent. The serial interrupt is executed, because the RI flag
was set or because the TI flag was set--or because both flags were set. The, ISR must
check the status of these flags to determine what action is appropriate. The 8051 does
not automatically clear the RI and TI flags and it can be clear by interrupt handler.
3.Explain the memory organization of 8051 microcontroller.

The 8051 microcontroller has two types of
memory Program Memory
Data Memory
The separation of code and data memory in the 8051 is different from the usual Von
Neumann architecture, which defines that code and data can share the common
memory.
The separated memory architecture is referred to as Harvard architecture.
Program Memory:
Program memory – 64 KB of program memory includes the 4KB of the on- chip
ROM. If the address exceeds 0FFF H, it will access the external program memory.
The processor will come to know whether the user wants to use the Internal ROM or
not from the EA(active low) pin. If this pin is pulled low, it means that the user does
not want to use the Internal ROM available. The processor will 0000H-FFFFH from
the external Program Memory. If this pin is held high, the processor will access
0000H - 0FFFH from the Internal ROM and as address goes above 0FFFH, it will
access the external Program Memory that is interfaced it
If EA (active low)= 5V
Internal Program Memory (ROM) =0000H-0FFFH (4KB)

External Program Memory=1000H-FFFFH(60KB)
If EA (active low)= 0V
External Program Memory=0000H-FFFFH(64KB)
Data Memory:
Data memory – 64 KB of external data memory and 128 bytes of internal data RAM
and 21 special function registers. For accessing the external data memory, the
processor can either issue an 8 bit address or a 16 bit address. To access the internal
data memory, the 8 bit address is used. This 8 bit address can provide address space
for 256 locations. The lower 128 addresses (0 – 127) are used as 128 bytes on chip
RAM. The upper part of the address space (128-255) is used to address the various
SFR. The Lowest 32 bytes (0-31) are reserved for 4 banks of 8 r gister each R0-
R7,out of which one bank may be used at any time. The working bank is specified in
two bits of the Program Status Word.
4. Explain the port operation in 8051 microcontroller. (Nov/Dec 2015)
(May/June 2015)
I/O Port Configuration

Each port of 8051 has bidirectional capability. Port 0 is called 'true bidirectional port' as it
floats (tristated) when configured as input. Port-1, 2, 3 are called 'quasi bidirectional port'.
Port-0 Pin Structure Port-0
has 8 pins (P0.0-P0.7).
The structure of a Port-0 pin is shown in fig 1
Fig 1: Port-0 Structure

Port-1 Pin Structure:
Port-1 has 8 pins (P1.1-P1.7) .

The structure of a port-1 pin is shown in fig 2.
Fig 2 Port 1 Structure

Port-1 does not have any alternate function. It is dedicated only for I/O interfacing. When
used as output port, the pin is pulled up or down through internal pull-up. To use port-1 as
input port, '1' has to be written to the latch. In this input mode when '1' is written to the pin
by the external device then it read. When '0' is written to the pin by the external device then
the external source must sink current due to internal pull-up. If the external device is not
able to sink the current the pin voltage may rise, leading to a possible wrong reading. Port-
2 has 8-pins (P2.0-P2.7) .

Port-2 is used for higher external address byte or a no mal input/output port. The I/O
operation is similar to Port-1. Port-2 latch remains stable wh n Port-2 pin are used for
external memory access. Due to internal pull-up there is limited curr nt driving capability.
PORT 3 Pin Structure:

Port-3 has 8 pin (P3.0-P3.7) . Port-3 pi s have alternate functions.

Each pin of Port-3 can be individually programmed for I/O operation or for alternate
function.
The alternate function can be activated only if the corresponding latch has been written to
'1'.
To use the port as input port, '1' should be written to the latch. This port also has internal
pull-up and limited current driving capability.
5.Draw the pin diagram of 8051 microcontroller and explain its port structure.
Port 0(p0.0 to p0.7):

It is 8-bit bi-directional I/O port. It is bit/ byte addressable. During external memory
access, it functions as multiplexed data and low-order address bus AD0-AD7.
Port 1 (p1.0 to p1.7):

It is 8-bit bi-directional I/O port. It is bit/ byte addressable. When logic '1' is written into
port latch then it works as input mode. It functions as simply I/O port and it does not have
any alternative function.
Port 0(p0.0 to p0.7):

It is 8-bit bi-directional I/O port. It is bit/ byte addressable. During external memory
access, it functions as multiplexed data and low-order address bus AD0-AD7.
Port 1 (p1.0 to p1.7):

It is 8-bit bi-directional I/O port. It is bit/ byte addressable. When logic '1' is written into
port latch then it works as input mode. It functions as simply I/O port and it does not have
any alternative function.
Port 2 (p2.0 to p2.7):

It is 8-bit bi-directional I/O port. It is bit/ byte addressable. During external memory access
it functions as higher order address bus (A8-A15).
Port 3(p3.0 to port 3.7):

It is 8-bit I/O port. In an alternating function each pins can be used as a special function I/O
pin.
P3.0-RxD:
It is an Input signal. Through this I/P signal microcontroller receives serial data of
serial communication circuit.
Fig: Pin Diagram of 8051 Microcontroller
P3.1-TxD:
It is O/P signal of serial port. Through this signal data is transmitted.
P3.2- (INT0):
It is external hardware interrupt I/P signal. Through this user, programmer or
peripheral interrupts to microcontroller.
P3.3-(INT1):
It is external hardware interrupt I/P signal. Through this user, programmer or
peripheral interrupts to microcontroller.
P3.4- T0:
It is I/P signal to internal timer-0 circuit. External clock pulses can connects to timer-
0 through this I/P signal.
P3.5-T1:
It is I/P signal to internal timer-1 circuit. xternal clock pulses can connects to timer-1
through this I/P signal.
P3.6-WR:
It is active low write O/P control signal. During External RAM (Data memory)
access it is generated by microcontroller. when [WR(bar)]=0, then performs write
operation.
P3.7- RD:
It is active low read O/P control signal. During External RAM (Data memory) access
it is generated by microcontroller. when [RD(bar)]=0, then performs read operation
from external RAM.
XTAL1 and XTAL2:
These are two I/P line for on-chip oscillator and clock generator circuit. A resonant
network as quartz crystal is connected between these two pin. 8051 microcontroller
also drives from external clock, then XTAL2 is used to drive 8051 from external
clock and XTAL1 should be grounded.
EA/VPP:
It is and active low I/P to 8051 microcontroller. when (EA)= 0, then 8051
microcontroller access from external program memory (ROM) only. When (EA) = 1,
then it access internal and external program memories (ROMS).
PSEN:
It is active low O/P signal. It is used to enable exte nal p ogram memory (ROM).
When [PSEN(bar)]= 0, then external program memory b comes enabled and
microcontroller read content of external memory location. Ther fore it is connected
to (OE) of external ROM. It is activated twice every external ROM memory cycle.
ALE:
Address latch enable: It is active high O/P signal. When it goes high, external
address latch becomes enabling and lower address of external memory (RAM or
ROM) latched into it. Thus it separates A0-A7 ddress from AD0-AD7. It provides
properly timed signal to latch lower byte addr ss. The ALE is activated twice in
every machine cycle. If external RAM & ROM is not accessed, then ALE is
activated at constant rate of 1/6 oscillator frequency, hich can be used as a clock
pulses for driving external devices.
RESET:
It is active high I/P signal. It should be maintained high for at least two machine
cycle while oscillator is running then 8051 microcontroller resets.
UNIT- IV PERIPHERAL INTERFACING
PART - A
1. Bring about the features of 8259.(May/June-2014)
It is a programmable interrupt controller. It manages eight interrupt requests.

2. The interrupt vector addresses are programmable. 3. The priorities of interrupts are
programmable. 4. The interrupt can be masked or unmasked individually
2. How data is transmitted in asynchronous serial communication?

(May/June-2014)
In asynchronous data transfer, one character s transferred at a time. Start and

stop bits are used with each character. The transmitter and receiver use two separate
clock inputs here.
3. What are the internal registers available 8259 PIC? (Apr/May-2015)
 Interrupt mask register (IMR),

 Interrupt Request register(IRR),
 In service register(ISR) and
 Priority register(PR)
4. Distinguish between synchronous and asynchronous transmission.

(Apr/May-2015)
Asynchronous synchronous
In this ,a word or character is preceeded by a In this, the transmission begins

with a block header,
Start bit and is followed by a stop bit. Which is a sequence of bits.
Data can be sent one character at a time used for transferring large
amount of data
5. What are the functions of USART? (Nov/Dec-2014)
USART stands for universal Synchronous / Asynchronous Receiver /

Transmitter. It is a programmable communication interface that can communicate by
using either synchronous or asynchronous serial data.
6. What is scan counter in 8279? (Nov/Dec-2012)
The scan counter has two modes to scan the key matrix and refresh the display.
In the encoded mode, the counter provides binary count that is to be externally decoded
to provide the scan linesfor keyboard and display. In the decoded scan mode, the
counter internally decodes the least significant 2 bit and provides a decoded 1 out of 4
scan on SL3-SL 3. The keyboard and display both are in the same mode at a time.
7. What are the basic modes of operations of 8255? (Nov/Dec-2013)
a) I/O Mode i. Mode 0- Simple Input/Output. ii. Mode 1- Strobe Input/Output
(handshake mode) iii. Mode 2- Strobe bi-directional mode b) Bit Set/Reset Mode.
8. List out the operating modes in 8253 Timer/Counter. (Nov/Dec-2014)
Mode 0 : Interrupt on terminal count
MODE 1 : Hardware Retriggerable One-shot
MODE 2 : Rate generator
MODE 3 : Square Wave Rate Generator
MODE 4 : Software Triggered Strobe.
MODE 5 : Hardware triggered strobe (Retriggerable).

9. Give the control word format of 8253 Timer. (May/June-2012)
10. What is BSR mode in 8255? (Nov/Dec-2012)
11. What are the different peripheral interfacing used with 8085
microprocessor? (May/June-2013)
Keyboard, Memory, EPROM, LCD display, LED seven segment displays.

12. What are the output terminals in USART 8251? (May/June-2013)
TXD (output terminal),

TXRDY (output terminal),
TXEMPTY (Output terminal),
RXRDY (Output terminal),
DTR (Output terminal),
RTS (Output terminal)
13. What are the different types of command words used in 8259A? (Nov/Dec-2013)
The command words of 8259A are classified in two groups
1. Initialization command words (ICWs)
2. Operation command words (OCWs)
14. What are the basic modes of operation of 8255? (Nov/Dec-2013)
Mode 0: Basic Input/output
Mode 1: Strobes Input/output
Mode 2: Bi-direction bus.
15. How data is transmitted in synchronous serial communication? (May/June-

2014)
In this the data is transferred bit by bit that is used for one to one communication.
16.What are the different types of ADC?
The different types of ADC are successive approximation ADC, counter type
ADC flash type ADC, integrator converters and voltage to- frequency converters.
17.What is the necessity of interfacing DAC with microcontroller? (Nov/Dec 2014)
In many applications, the microcontroller has to produce analog signals for

controlling certain analog devices. Basically, the microcontroller can produce only
digital signals. In order to convert the digital signal to analog signal a Digital to
Analog Converter has to be employed.
18. What is the jump range? (Nov/Dec2015)

 AJMP addr11 (Absolute Jump) – Within 2K bytes of program memory.
 LJMP addr16 (Long Jump) -Within 64K bytes of program memory.
 SJMP Rel.addr (Short Jump) –128 to +127 of program memory
19. What is a serial data buffer?
Serial data buffer is a special function register and it initiates serial transmission when byte
is written to it and if read, it reads received serial data. It contains two independent
registers internally. One of them is a transmit buffer, which is a parallel-in serial-out
register. The other is a receive buffer, which is a serial-in parallel-out register
20. What are timer registers?
Timer registers are two 16-bit registers and can be accessed as their lower and upper bytes.
TLO represents the lower byte of the timing register 0, while THO represents higher bytes
of the timing register 0. Similarly, TLI and THI represent lower and higher bytes of timing
register 1. These registers can be accessed using the addresses allotted to them, which lie in
the special function registers address range, i.e., 801 H to FF.
21. What is the use of timing and control unit?
Timing and control unit is used to derive all the necessary timing and control signals
required for the internal operation of the circuit. It also derives control signals that are
required for controlling the external system bus.
22. When are timer overflow bits set and reset?
The timer overflow bits are set when timer rolls over and reset either by the execution of an
RET instruction or by software, manually clearing the bits. The bits are located in the
TCON register along with timer run control (TRn) bits
23. Explain the mode (0 and1) operation of the timer.(April/May2012)

The operations are as follows:
 Timer mode 0 and 1 operations are similar for the 13 bit (mode) or 16 bit (mode 1)
counter. When the timer reaches the limits of the count, the overflow flag is set and
the counter is reset back to zero. The modes 0 and 1 can be used to time external
events.
 They can be used as specific time delays by loading with an initial value before
allowing them to execute and overflow
24. What is the different modes in which timer 2 can operate?
The two different modes in which Tmer 2 operates are.

i. Capture mode: Timer 2 operates as free running clocks, which saves the timers value on
each high to low transition. It can be used for recording bit lengths when receiving
Manchester-encoded data.
ii. Auto-reload mode: When the timer overflows, value is written into TH2/TL2
registers from RCA P2H/RCA P21 registers. This feature is used to implement a system
watch dog timer.
25. What is the use of a watch dog timer?
A watching timer is used to protect an application in case the controlling microcontroller

begins to run amok and execute randomly rather than the preprogrammed instructions
written for the application.
PART - B
1.Draw the block diagram of 8255A Programmable Peripheral Interface
(PPI) and explain each block . (May/June-2014)
The Programmable Peripheral Interface (PPI) chip is a peripheral chip.It is made in 40 pin
DIP. The 8255 is used to give the CPU access to programmable parallel I/O.. The 8255 has
24 input/output pins in all.These are divided into three 8-bit ports.
Port A and port B can be used as 8-bit input/output ports.Port C can be used as an 8-bit
input/output port or as two 4-bit input/output ports or to produce handshake signals for ports
A and B.
The three ports are further grouped as follows:
1. Group A consisting of port A and upper part of port C.

2. Group B consisting of port B and lower part of port C.
Eight data lines (D0 - D7) are available to read/write data into the ports or control
register.The RD andWR pin , which are active low signals for read and write operations.
The address lines A1 and A0 allow to successively access any one of the ports or the control
register.The control signal chip select CS is used to e able the 8255 chip. when CS = '0', the
8255 is enabled.The RESET input is connected to the RESET pin8085.When the system is
reset, all the ports are initialized as input lines.
The control register or the command word register is an 8-bit register used to select the modes of
operation and input/output designation of the ports.
Operational modes of 8255
There are two basic operational modes of 8255:
 Bit set/reset Mode (BSR Mode).

 Input/Output Mode (I/O Mode).
Bit set/reset (BSR) mode

The Bit Set/Reset (BSR) mode is applicable to port C only.Each line of port C (PC0 - PC7) can
be set/reset by suitably loading the control word register. BSR mode and I/O mode are
independent and selection of BSR mode does not affect the operation of other ports in I/O mode.
A1 A0 Port Selected
0 0 Port A
0 1 Port B
1 0 Port C
1 1 Control Word Register
BLOCK DIAGRAM OF INTEL 8255:

CONTROL WORD FOR BSR MODE:
D7 D6 D5 D4 D3 D2 D1 D0
0 * * * B2 B1 B0 S/R
D7 bit is always 0 for BSR mode.

Bits D6, D5 and D4 are don't care bits.
Bits D3, D2 and D1 are used to select the pin of Port C.
Bit D0 is used to set/reset the selected pin of Port C.
Selection of port C pin is determined as follows:

B B B
2 1 0 Pin of Port C Selected
0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7
INPUT/OUTPUT MODE
This mode is selected wh n D7 bit of the Control Word Register is 1. There are three
I/O modes
1. Mode 0 - Simple I/O

2. Mode 1 - Strobed I/O
3. Mode 2 - Strobed Bi-directional I/O
Mode 0 - Simple I/O
In this mode, the ports can be used for simple I/O operations without handshaking
signals.
Port A- 8 bit port.
Port B – 8 bit port.
Port C – two 4 bit ports.(Port C upper & Port C lower)
Mode 0 features:
Output ports are latched.Input ports are buffered, not latched.Ports do not have
handshake or interrupt capability.With 4 ports, 16 different combinations of I/O are
possible.
Mode 1:- Strobed I/O
Port A or Port B for handshake (strobed) input or output operation.
Port A + Port C upper function as handshake signals.
Port B + Port C lower function as handshake signals.
Mode 1 features:
Two ports i.e. port A and B can be used as 8-bit i/o ports.Each port uses three lines
of port c as handshake signal and remaining two signals can be used as i/o
ports.Interrupt logic is supported.Input and Output data are latched.
Input Handshaking signals
1. IBF (Input Buffer Full)

2. STB (Strobed Input)
3. INTR (Interrupt request)
4. INTE (Interrupt enable)
Output Handshaking signals
1. OBF (Output Buffer Full)

2. ACK (Acknowledge)
3. INTR (Interrupt request)
4. INTE (Interrupt enable)
Mode 2:Strobed Bidirectional I/O

Port A can be used for bidirectional handshake data transfer. Pins PC4 - PC7 are used
as handshake lines for port A.Acknowledgement and handshaking signals are
provided to maintain proper data flow and synchronization between the data
transmitter and receiver.
2.Discuss the internal architecture of 8253/8254 Programmable Interval timer.

(May/June-2014)
The Intel 8253 and 8254 are Programmable Interval T mers (PITs), which perform
timing and counting functions and has the same pinout.
8253 8254
Operating frequency is 0-2.6 Mhz. Operating frequency is 0-10 Mhz.
Uses N-MOS technology. Uses H-MOS technology.
Read Back command is not available. Read Back command is available.

Reads and Writes of the same counter Reads and Writes of the same counter
cannot be interleaved can be interleaved
BLOCK DIAGRAM OF INTEL 8253/8254
The timer has three counters.or timers which are named as "Counter 0", "Counter 1" and
"Counter 2".Each counter has 2 input pins – "CLK" (clock input) and "GATE" – and 1-pin,
"OUT", for data output. The 3 counters are 16-bit down counters independent of each other,
and can be easily re d by the CPU. The first counter is used to generate atimekeeping
interrupt.The s cond counter is used to trigger the refresh of DRAM memory. The last
counter is used to generate tones via the PC speaker.
Data/Bus Buffer:
This block contains the logic to buffer the data bus to / from the microprocessor, and to the
internal registers. It has 8 input pins, usually labelled as D7..D0, where D7 is the MSB.
Read/Write Logic:
The Read/Write Logic block has 5 pins.
 /RD: read signal

 /WR: write signal
 /CS: chip select signal
 A0, A1: address lines
Control Word Register:

To initialize the counters, the microprocessor must write a control word (CW) in this register.
This can be done by setting proper values for the pins of the Read/Write Logic block and then
by sending the control word to the Data/Bus Buffer block.The control word register contains
8 bits, labeled D7..D0 (D7 is the MSB).
D7 D6 D5 D4 D3 D2 D1 D0
SC1 SC2 RW1 RW0 M2 M1 M0 BCD

Operation Modes
Mode 0 : Interrupt on Terminal Count

Mode 0 is used for the generation of accurate time delay under software control. In this mode,
the counter will start counting from the initial COUNT value loaded into it, down to
0.Counting rate is equal to the input clock frequency.The OUT pin is set low after the Control
Word is written, and counting starts one clock cycle after the COUNT programmed. OUT
remains low until the counter reaches 0, at which point OUT will be set high until the counter
is reloaded or the Control Word is written. The Gate signal should remain active high for
normal counting. If Gate goes low counting gets terminated and current count is latched till
Gate pulse goes high again.
Mode 1 : Programmable One Shot

In this mode 8253 can be used as Monostable Multivibrator.GATE input is used as trigger
input.OUT will be initially high. OUT will go low on the CLK pulse following a trigger to
begin the one-shot pulse, and will remain low until the Counter reaches zero. OUT will then
go high and remain high until the CLK pulse after the next trigger.
Mode 2: Rate Generator

In this mode, the device acts as a divide-by-n counter, which is commonly used to generate a
real-time clock interrupt.Counting process will start the next clock cycle after COUNT is
sent. OUT will then remain high unt l the counter reaches 1, and will go low for one clock
pulse.OUT will then go high again, and the whole process repeats itself.
Mode 3 : Square Wave Generator

This mode is similar to mode 2. The duration of the high and low clock pulses of the output
will be different from mode 2.If „N „is the number loaded into the counter , the output will be
High for N/2 counts and N/2 counts for Low if N is Even.
High for (N+1)/2 counts and (N-1)/2 counts for Low if N is Odd.
Mode 4 : Soft are Triggered Strobe

After Control Word and COUNT is loaded, the output will remain high until the counter
reaches zero.The counter will then generate a low pulse for 1 clock cycle (a strobe) – after
that the output will become high again.
Mode 5 : Hardware Triggered Strobe

This mode is similar to mode 4. However, the counting process is triggered by the GATE
input.After receiving the Control Word and COUNT, the output will be set high.
When the GATE input is high , it will start counting. When the counter reaches 0, the output
will go low for one clock cycle – after that it will become high again, to repeat the cycle.
3.Draw and explain the functional block diagram of 8259 Programmable Interrupt
Controller. (Apr/May-2015)
Functional Description:
The 8259 A has eight interrupt request inputs, IR0- IR7.The 8259 A uses its INT output to
interrupt the 8085A via INTR pin.The 8259Areceives interrupt acknowledge pulses from the
at its input.Vector address used by the 8085 A to transfer control to the service subroutine of
the interrupting device, is provided by the 8259 A on the data bus.
The 8259A is a programmable device that must be in t al zed by command words sent by the.
After initialization the 8259A mode of op ration can be changed by operation command
words.
The descriptions of various blocks are,
Data bus buffer:
This 3- state, bidirectional 8-bit buffer is used to interface the 8259Ato the system data bus.
Control words and status information are transferred through the data bus buffer.
Read/Write & control logic:

The function of this block is to accept OUTPUT commands from the CPU. It contains the
initialization command word (ICW) register and operation command word OCW) register
which store the various control formats for device operation. This function block also allows
the status of 8259A to be transferred to the data bus.
Interrupt request register (IRR):
IRR stores all the interrupt inputs that are requesting service.It keeps track of which interrupt
inputs are asking for service. If an interrupt input is unmasked, and has an interrupt signal on
it, then the corresponding bit in the IRR will be set.
Interrupt mask register (IMR):
The IMR is used to disable (Mask) or enable (Unmask) individual interrupt inputs.Each bit in
this register corresponds to the interrupt input with the same number.The IMR operation on
the IRR. Maskingof higher priority i put will not affect the interrupt request lines oflower
priority.To unmask any interrupt the corresponding bit is set „0‟.
In service register (ISR):

The in service registers keeps tracks of which interrupt inputs are currently being
serviced.For each input that is cu ently being serviced the corresponding bit will be set in the
in service register.E ch of these 3-reg can be read as status reg.Priority Resolver:
This logic block determines the priorities of the set in the IRR. The highest priority is
selected and strobed into the corresponding bit of the ISR during pulse.
Cascade buffer/comparator:
This function blocks stores and compare the address of all 8259A‟s in the register.The
associated 3-I/O pins (CAS0-CAS2) are outputs when8259A is used a master.As a master,
the 8259A sends the ID of the interrupting slave device onto the cas2-cas0.The slave thus
selected will send its pre-programmed subroutine address on to the data bus.
Priority Modes of 8259 :
The priority modes availaible in 8259 is
 Fully Nested Mode

 Automatic Rotation Mode
 Specific Rotation Mode
Fully Nested Mode:
This is a general purpose mode in which all IR‟s are arranged from highest to lowest
ie.IR0 is the highest and IR7 is the lowest one.Any IR can be assigned the highest priority,the
priority sequence will begin at that IR.
Automatic Rotation Mode:
In this mode, a device which one is being serviced will be considered as a lowest priority
In the next time.
Specific Rotation Mode:
This mode is similar to the automatic rotation mode except the user can select any IR for
the lowest priority, thus fixing any other priorities.
End of Interrupts (EOI):
After the completion of an interrupt serv ce, the corresponding ISR bit needs to be
reset.This is called the End of Interrupt.(EOI).It can be issued in 3 formats.They are
Non Specific EOI Command:
When the 8259 receives this command,it resets the highest priority ISR bit.
Specific EOI Command:
It specifies which ISR bit to be reset.
Automatic EOI Command:
When the 8259 receives the third INTA signal, the ISR bit is reset.The major drawback
of this mode is that ISR does not have information on which IR is being serviced.
There are four Initialization Command Word ICW1,ICW2,ICW3&ICW4 and three
Operation Control Word OCW1,OCW2 &OCW3
Initialization Command Word 1 (ICW1)
4.Draw the neat diagram ,explain the architecture and features of 8279
keyboard / display controller. (Apr/May-2015)
Block Diagram of Keyboard/Display Controller
The Keyboard/Display Controller 8279Intel‟s 8279 is a general purpose Keyboard Display

controller that simultaneously drives the display of a system and interfaces a Keyboard with
the CPU. The Keyboard Display interface scans the Keyboard to identify if any key has been
pressed and sends the code of the pressed key to the CPU.It also transmits the data received
from the CPU,to the display device.The Keyboard display controllerchip8279provides1. A
set of four scan lines and eight return lines for interfacingkeyboards.2. A set of eight output
lines for interfacing display.
I/OControlandDataBuffer
The I/O control section controls the flow of data to/from the 8279. The data buffer interface
the external bus of the system with internal bus of 8279. The pin Ao, RD and WR select the
command, status or data read/write operat ons carried out by the CPU with 8279.
Control and Timing Register and Timing Control
These registers store the keyboard and display modes and other operating conditions
programmed by CPU.The registers are written with Ao=1 and WR =0.The timing and control
unit controls the basic timings for the operation of the circuit.Scan Counter divide down the
operating frequency of 8279 to derive scan keyboard and scan display frequencies.
Scan Counter
The Scan Counter has two modes to scan the key matrix and refresh the display.In the
Encoded mode, the counter provides a binary count that is to be externally decoded to
provide the scan lines for keyboard and display.In the decoded scan mode, the counter
internally decodes the least significant 2 bits and provides a decoded 1 out of 4 scan on SL0-
SL3.The Keyboard and Display both are in the same mode at a time.
Return Buffers and Keyboard Debounce and Control

This section scans for a Key closure row-wise.If it is detected, the Keyboard debounce unit
debounces the key entry.After the debounce period, if the key continues to be detected. The
code of the Key is directly transferred to the sensor RAM along with SHIFT and CONTROL
key status.
FIFO/Sensor RAM and Status Logic

In Keyboard or strobed input mode, this block acts as 8-byte first-in-first-out (FIFO) RAM.
Each key code of the pressed key is entered in the order of the entry, and in the meantime,
read by the CPU, till the RAM becomes empty. The status logic generates an interrupt
request after each FIFO read operation till the FIFO is empty.In scanned sensor matrix mode,
this unit acts as sensor RAM.Each row of the sensor RAM is loaded with the status of the
corresponding row of sensors in the matrix.If a sensor changes its state, the IRQ line goes
high to interrupt the CPU.
Display Address Registers and Display RAM.

The Display address registers hold the addresses of the word currently being written or read
by the CPU to or from the display RAM.The contents of the registers are automatically
updated by 8279 to accept the next data entry by CPU. The 16-byte display RAM contains
the 16-byte of data to be displayed on the sixteen 7-seg displays in the encoded scan mode.
Details of Modes of Operation

Keyboard Modes
Scanned Keyboard Mode with 2 Key Lockout
In this mode of operation, when a key is pressed, a debounce logic comes into operation. The
Key code of the identified key is entered i to the FIFO with SHIFT and CNTL status,
provided the FIFO is not full.
Scanned Keyboard with N-key Rollover

In this mode, each key depression is treated independently. When a key is pressed, the
debounce circuit waits for 2 keyboard scans and then checks whether the key is still
depressed. If it is still depressed, the code is entered in FIFO RAM. Any number of keys can
be pressed simultaneously and recog ized in the order, the Keyboard scan record them.
Scanned Keyboard Special Er o Mode

This mode is valid only under the N-Key rollover mode. This mode is programmed using end
interrupt/error mode s t command. If during a single debounce period (two Keyboard scan)
two keys are found pressed, this is considered a simultaneous depression and an error flag is
set. This flag, if set, prevents further writing in FIFO butallows generation of further
interrupts to the CPU for FIFO read.
Sensor Matrix Mode

In the Sensor Matrix mode, the debounce logic is inhibited the 8-byte memory matrix. The
status of the sensor switch matrix is fed directly to sensor RAM matrix Thus the sensor RAM
bits contains the row-wise and column-wise status of the sensors in the sensor matrix.
DisplayModes
There are various options of data display The first one is known as left entry mode or type
writer mode. Since in a type writer the first character typed appears at the left-most position,
while the subsequent characters appears successively to the right of the first one.The other
display format is known as right entry mode, or calculator mode, since the calculator the first
character entered appears at the right-most position and this character is shifted one position
left when the next character is entered.
1.LeftEntryMode
In the Left entry mode, the data is entered from the left side of the display unit. Address0 of the
display RAM contains the leftmost display character and address 15 of the RAM contains the
rightmost display character.
2.RightEntryMode
In the right entry mode, the first entry to be displayed is entered on the rightmost display.The
next entry is also placed in the right most display but after the previous display is shifted left
by one display position.
All the Command words or status words are written or read with Ao = 1 and CS = 0 to or from
8279.
a. Keyboard/ Display mode s t
The format of the command word to select different modes of operation of 8279 is given below
with its bit definitions.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 D D K K K
5.Draw the neat diagram ,explain the architecture and features of 8237Direct
Memory Access
Controller.
DMA Controller: A DMA controller is a device, usually peripheral to a CPU that is
programmed to perform a sequence of data transfers on behalf of the CPU.A DMA
controller can directly access memory and is used to transfer data from one memory
location to another, or from an I/O device to memory and vice versa.A DMA controller
manages several DMA channels, each of which can be programmed to perform a sequence
of these DMA transfers.A DMA request signal for each channel is routed to the DMA
controller.When the DMA controller sees a DMA request, it responds by performing one or
many data transfers from that I/O device into system memory or vice versa.Channels must
be enabled by the processor for the DMA controller to respond to DMA requests.A DMA
controller typically shares the system memory and I/O bus with the CPU and has both bus
master and slave capability. The d agram of DMA controller architecture and how the DMA
controller interacts with the CPU.In bus master mode, the DMA controller acquires the
system bus (address, data, and control lines)from the CPU to perform the DMA transfers.
Because the CPU eleases the system bus for the duration of the transfer, the process is
sometim s r f rred to as cycle stealing.In bus slave mode, the DMA controller is access d by
the CPU, which programs the DMAcontroller's internal registers to set up DMA
transfers.The internal registers consist of source and destination address registers and
transfer count registers for each DMA channel, as well as control and status registers for
initiating, monitoring, and sustaining the operation of the DMAcontroller.
DMA Transfer Types and Modes :
DMA controllers vary as to the type of DMA transfers and the number of DMA channels.
The two types of DMA transfers are
i) flyby DMA transfers
ii) fetch-and-deposit DMAtransfers.
iii) The three common transfer modes are single, block, and demand transfer modes.
A 8237 DMA controller IC :

CLK: CLOCK INPUT:
The Clock Input is used to generate the timing signals which control82C37A
operations.
CS: CHIP SELECT:

Chip Select is an active low input used to enable the controller onto thedata bus for
CPU communications.
Fig:Architecture of DMA Controller
RESET:
This is an active high input which clears the Command, Status, Request, and
Temporary registers, the First/Last Flip-Flop, and the mode register counter.The Mask
registeris set to ignore requests.
READY:
This signal can be used to extend the memory read and write pulses from the
82C37A to accommodate slow memories or I/O devices.
HLDA: HOLD ACKNOWLEDGE:
The active high Hold Acknowledge from the CPU indicates that it has relinquished
control of the system busses.
DREQ0-DREQ3: DMA REQUEST:

The DMA Request (DREQ) lines are individual asynchronous channel request
inputs used by peripheral circuits to obtain DMA service.In Fixed Priority, DREQ0 has the
highest priority and DREQ3 has the lowest priority.A request is generated by activating the
DREQ line of a channel. DACK will acknowledge the recognition of a DREQ
signal.RESET initializes these lines to active high.DREQ must be maintained until the
corresponding DACK goes active.DREQ will not be recognized while the clock is
stopped.Unused DREQ inputs should be pulled High or Low(inactive) and the
corresponding mask bit set.
DB0-DB7: DATA BUS:

The Data Bus lines are bidirectional three-state signals connected to the system
data bus. The outputs are enabled in the Program condition during the I/O Read to output
the contents of a register to the CPU.The outputs are disabled and the inputs are read
during an I/O Write cycle when the CPU is programming the 82C37A control registers.
During DMA cycles, the most significant 8-bits of the address are output onto the data bus
to be strobed into an external latch by ADSTB. In memory-to-memory operations, data
from the m mory enters the 82C37A on the data bus during the read-from-memory transfer,
then during the write-to memory transfer, the data bus outputs write the data into the new
memory location.
IOR: READ:
I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an
input control signal used by the CPU to read the control registers. In the active cycle, it is
an output control signal used by the 82C37A to access data from the peripheral during a
DMAWrite transfer.
IOW: WRITE:
I/O Write is a bidirectional active low three-state line.
In the Idle cycle, it is an input control signal used by the CPU to load information into
the 82C37A. In the active cycle, it is an output control signal used by the 82C37A to
load data to the peripheral during a DMA
Read transfer.
EOP: END OF PROCESS:

End of Process (EOP) is an active low bidirectional signal The 82C37A allows an
external signal to terminate an active DMA service by pulling the EOP pin low.A pulse is
generated by the 82C37A when terminal count (TC) for a y channel is reached, except for
channel 0 in memory-to-memory mode.During memo y-to-memory transfers , EOP will be
output when the TC for channel 1 occurs.The EOP pin is driven by an open drain transistor
on-chip, and requires an external pull-up r sistor to VCC. When an EOP pulse occurs,
whether internally or externally generated, the 82C37A will terminate the service,and if
auto-initialize is enabled, the base registers will be written to the current registers of that
channel. The mask bit a d TC bit in the status word will be set for the currently active
channel by EOP unless the channel is programmed for auto initialize. In that case, the mask
bit remains clear.
A0-A3: ADDRESS: The four l ast significant address lines are bidirectional three-state
signals. In the Idle cycle, they are inputs and are used by the 82C37A to address the
control register to be loaded or read. In the Active cycle, they are outputs and provide
the lower 4-bits of the output
address.
A4-A7: ADDRESS: The four most significant address lines are three-state outputs and
provide 4-bits of address. These lines are enabled only during the DMA service.
HRQ: HOLD REQUEST: The Hold Request (HRQ) output is used to request control
of the system bus. When a DREQ occurs and the corresponding mask bit is clear, or
a software DMA request is made, the 82C37A issues HRQ. The HLDA signal then
informs the controller when access to the system busses is permitted. For stand-alone
operation where the 82C37A always controls the busses, HRQ may be tied to
HLDA. This will result in one S0 state before the transfer.
DACK0-DACK3: DMA ACKNOWLEDGE:

DMA acknowledge is used to notify the individual peripherals when one has been
granted a DMA cycle. RESET initializes them to active low.
AEN: ADDRESS ENABLE:

Address Enable enables the 8-bit latch containing the upper 8address bits onto the
system address bus. AEN can also be used to disable other system busdrivers during
DMA transfers.AEN is active high.
ADSTB: ADDRESS STROBE:
This is an active high signal used to co trol latching of the upper address byte.
During block operations, ADSTB will only be issued when the upper address byte
must be updated. ADSTB timing is refe e ced to the falling edge of the 82C37A
clock.
MEMR: MEMORY READ:

The Memory Read signal is an active low three-state output used to access data from
the selected memory location during a DMA Read or a memory-to-memory transfer.
MEMW MEMORY WRITE:

The Memory Write signal is an active low three-state output used to write data to the
selected memory location during a DMA Write or a memory-to-memory transfer.
NC: NO CONNECT: Pin 5 is open and should not be tested for continuity.
Functional Description
The 82C37A direct memory access controller is designed to improve the data
transfer rate in systems which must transfer data from an I/O device to memory, or move a
block of memory to an I/O device. It will also perform memory-to-memory block moves, or
fill a block of memory with data from a single location. Operating modes are provided to
handle single byte transfers as well as discontinuous data streams, which allows the
82C37A to control data movement.Memory-to-memory operations require temporary
internal storage of the data byte between generation of the source and destination addresses,
so memory-to-memory transferstake place at less than half the rate of I/O operations, but
still much faster than with centralprocessor techniques. The block diagram of the 82C37A
consists of timing and control block, priority block, and internal registers are the main
components. The timing and control block derives internal timing from clock input, and
generates ext rnal control signals. The Priority Encoder block resolves priority contention
betw n DMA channels requesting service simultaneously.
DMA Operation:
In a system, the 82C37A address and control outputs and data bus pins are basically
connected in parallel with the system busses. An external latch is required for the upper
address byte. While inactive, the controller‟s outputs are in a high impedance state. When
activated by a DMAr quest and bus control is relinquished by the host, the 82C37A drives
the busses and generates the control signals to perform the data transfer.The operation
performed by activating one of the four DMA request inputs has previously been
programmed into the controller via the Command,Mode, Address, and Word Count
registers.For example, if a block of data is to be transferredfrom RAM to an I/O device, the
starting address of the data is loaded into the 82C37A Current and Base Address registers
for a particular channel, and the length of the block is loaded into the channel‟s Word Count
register. The corresponding Mode register is programmed for a memory to-I/O operation
(read transfer), and various options are selected by the Command register and the other
Mode register bits.The channel‟s mask bit is cleared to enable recognition of a DMArequest
(DREQ). The DREQ can either be a hardware signal or a software command. Once
initiated, the block DMA transfer will proceed as the controller outputs the data
address,simultaneous MEMR and IOW pulses, and selects an I/O device via the DMA
acknowledge(DACK) outputs.The data byte flows directly from the RAM to the I/O device.
After each byte is transferred, the address is automatically incremented (or decremented)
and the word count is decremented.The operation is then repeated for the next byte. The
controller stops transferring data when the Word Count register underflows, or an external
EOP is applied.
UNIT V
MICRO CONTROLLER PROGRAMMING & PPLICATIONS
PART -A
1. What are the applications of 8051 Microcontroll r? (M/J ‘12’)
(i) Washing Machine control,
(ii) Traffic Light control,
(iii)Servo Motor control,
(iv) Stepper motor control,
(v) DC motor control.
2.What are the 3 classes of data tra sfer instructions?

 General purpose transfer
 Accumulator specific transfer
 Address object transfer
3.What are the 3 classes of control transfer instruction?

 Unconditional calls, returns and jumps
 Conditional jumps
 Interrupts
4.Write about CALL statement in 8051?(Nov/Dec 2012)

There are two subroutine CALL instructions. They are
 *LCALL(Long CALL)
 *ACALL(Absolute CALL)
Each increments the pc to the 1st byte of the instruction & pushes them in to the stack.
5.Write about the jump statement?

There are three forms of jump. They are
LJMP(Long-jump)-address 16
AJMP(Absolute jump)-address 11
SJMP(short jump)-relative address
6.Write a program to find 2’s complement using 8051?

MOV A,R0
CPL A
INC A
7.Write a program to swap two numbers using 8051?
MOV A,#data
SWAP A
(i) Mention the interrupts of 8051 microcontroller? (Nov/Dec ‘13’)

INT0, TF0, INT1, TF1, R1 & T1
9.What is a stepper motor?(Nov/Dec 2014)

A stepper motor is a specially constructed DC motor with 4 windings. It rotates in
precise steps with a common step size range of 0.9 to 30 degrees.
10.Write the coil sequence for a full step rotation of a stepper motor.(May/June
2013)
11.What are the tasks involved in keyboard interfacing?

The task involved in keyboard interfacing are
Sensing a keyboard
Sensing a key actuation
De bouncing the key and
Generating key codes .
12. How a keyboard matrix is formed in keyboard interface ?

The return lines RL0 to RL7 of 8279 are used to form the columns of keyboard matrix and
decoded scan the scan lines SLO to SL3 of 8279 are used to form the rows of keyboard matrix.
Inencoded scan mode, the output li es of external decoder are used as rows of keyboard matrix.
13. What is scanning in keybo rd and what is scan time?
The process of sending a z ro to each row of a keyboard matrix and reading the
columnsfor key actuation is called scanning. The scan time is the time taken by the
processor to scan allthe rows one by one starting from first row and coming back to
the first row.
14.Why a driver circuit is used while connecting a microprocessor to relay?

Microcontroller pin lacks sufficient current to drive the relay. So a driver circuit or
power transistor is placed between the microcontroller and the relay.
15.How the speed of an electric motor is controlled?

The speed of an electric motor is controlled by controlling the power source of the motor.
To provide a variable power supply, a variable series resistance is placed between the
motor and supply.
16. Explain the operating mode2 of 8051 serial ports? (April/May

2009&Nov/Dec2008)
In this mode 11 bits are transmitted(through TXD)or received(through RXD):a start bit(0),
8 data bits(LSB first),a programmable 9th data bit ,& a stop bit(1).ON transmit the 9th
data bit (TB* in SCON)can be assigned the value of 0 or 1.Or for eg:, the parity bit(P, in
the PSW)could be moved into TB8.On receive the 9thdatabit go in to the RB8 in Special
Function Register SCON, while the stop bit is ignored. The baud rate is programmable to
either 1/32or1/64 the oscillator frequency.
17. Explain the mode3 of 8051 serial ports? (April/May2008)
In this mode,11 bits are transmitted(through TXD)or received(through RXD):a start bit(0),
8 data bits(LSB first),a programmable9th data bit ,& a stop bit(1).In fact ,Mode3 is the
same as Mode2 in all respects except the baud rate. The baud rate in Mode3 is variable. In
all the four modes, transmission is initiated by any instruction that uses SBUF as a
destination register. Reception is initiated in Mode0 by the condition
RI=0&REN=1.Reception is initiated in other modes by the incoming start bit if REN=1.
18. Write a program to mask the 0th&7thbit using8051?
MOV A,#data
ANL A,#81
MOV DPTR,#4500
MOVX @DPTR,A
LOOP SJMP LOOP
19. Define baud rate. (May/June 2016)
Baud rate is used to indicate the rate at which data is being transferred.
Baud rate = 1/Time for a bit cell.
20. Mention the features of serial port in mode 0. (Nov/Dec2015)
In this mode serial enters and exits through RXD, TXD outputs the shiftclock. 8 bits are
transmitted /received 8 data bits first (LSB first).The baudrate is fixed at 1/12 the oscillator
frequency.
21. Which register is used for serial programming in 8051 microcontroller? Illustrate
it. (Apr/May2015)
SBUF Register (Serial Buffer):

SBUF is an 8-bit register for serial communication in 8051.For a byte of data to be
transferred via TxD line and holds the byte of data when it is received by 8051's RxD line.
SCON Register (Serial Control):
SCON is an 8 bit register used to program the start bit,stop bit and data bits of data framing
among other things.
22. How is A/D convertor interfaced with 8051? (Nov/Dec2015)
23.What is meant by nesting of interrupts?
Nesting of interrupts means that interrupts are re-enabled inside an interrupt handler. If
another interrupt request codes in, while the first interrupt handler is executing, processor
execution will acknowledge the new interrupt and jump to its vector.
24. How is the 8051 serial port different from other micro controllers?(Nov/Dec2013)
The 8051 serial port is a very complex peripheral and able to send data synchronously and
asynchronously in a variety of different transmission modes.
25. Explain synchronous data transmission.
 In synchronous mode (mode 0), the instruction clock is used.
 Data transfer is initiated by writing to the serial data port address.
 Txd pin is used for clock output, while Rxd pin is for data transfer.
 When a character is received, the status of the data transfer is monitored by

polling the RI-n bit in serial control register (SCON).
PART -B
1.Explain the different types of instruction of 8051. (May/June 2012)
8051 has about 111 instructions. These can be grouped into the following
categories.
1. .Data Transfer instructions

2. Arithmetic Instructions
3. Logical Instructions
4. Program Branching (Control transfer) Instruct o s
1.Data Transfer Instructions
The data transfer instruction is used to (copy) transfers data from source
location to destination location.
Syntax:
MOV Rn , Rn
Ex:MOV A,R0
This instruction transfers data from R0 register to Accumulator.
Syntax:
MOV A, direct
Ex:MOV A,40H
This instruction transfers data from 40H location to Accumulator.
Syntax:
MOV A, @Ri
Ex: MOV A, @R0
This instruction transfers data from the content of R0 as a location to Accumulator.
Syntax:
MOV A, #data
EX: MOV A, # 40H
This instruction transfers immediate data 40H to Accumulator.
2.Arithmetic Instructions:
Thearithmeticinstructionsincludesaddition,subtraction,multiplication,division,increment,d
ecrement and etc.
Syntax:
ADD Rn , Rn
Ex:ADD A,R0
This instruction adds data from R0 register and Accumulator and finally
result is stored in Acc.
Syntax:
ADD A, direct
Ex:ADD A,40H
This instruction adds data from 40H location and Accumulator and finally
Syntax:
ADD A, @Ri
Ex: ADD A, @R0
This instruction adds data from the content of R0 as a location and

Accumulator and finally result is stored in Acc..
Syntax:
ADD A, #data
EX: ADD A, # 40H
This instruction adds immediate data 40H a d Accumulator and finally

result is stored in Acc..
3.Logical Instructions
The logical instructions includes AND,OR,EXOR,Rotate instructions.
Syntax:
ANLRn , Rn
Ex:ANL A,R0
This instruction AND with data from R0register,Accumulator and finally

Syntax:
ANL A, direct
Ex:ANL A,40H
This instruction AND with data from 40H location,Accumulator and finally
Syntax:
ANL A, @Ri
Ex: ANL A, @R0
This instruction AND with data from the content of R0 as a

location,Accumulator and finally result is stored in Acc..
Syntax:
ANL A, #data
EX: ANL A, # 40H

This instruction AND immediate data 40H ,Accumulator and finally
result is stored in Acc..
5.Control Transfer Instructions
ACALL addr11
Absolute Call to relative address
AJMP addr11
Asolute Jump to relative address
CJNE A, direct, rel
Compare ith A ith memory location content if not equal then jump to relative address.
DJNZ Rn, rel
Decrement Rn, and jump if not zero to relative address
JC rel
Jump if carry to relative address
JNC rel
Jump if no carry to relative address
2.Explain in detail about 8051 Addressing Modes(May/June 2014)

8051 has four addressing modes.
1.Register Addressing.
2.Direct Addressing.
3.Register Indirect Addressing.
4.Immediate Addressing
5.Base plus Index Register Addressing.
1.Register Addressing:
This way of addressing accesses the bytes in the current register bank.
Data is available in the register spec f ed n the instruction.
The register bank is decided by 2 bits of ProgramStatusWord (PSW).
Example-
ADD A, R0
This instruction Adds content of R0 to A and stores in A
2.Direct Addressing:
The address of the data is available in the instruction.
Example -
MOV A, 88H;
Moves the content of address 88Hto A.
3.Register Indirect Addressing:

The address of data is available in the R0 or R1 registers as specified in
the instruction.
Example –
MOV A, @R0
Moves content of address pointed by R0 to A .
4.Immediate Addressing:
Data is immediately available in the instruction.
Example -
ADD A, #77H
Adds 77 H to A and stores in A
5.Base plus Index Register Addressing.

The content of base register and index register co te t is added to locate the
data.
Example -
MOVC A, @A+DPTR
Moves content of address pointed by A+DPTR to A
3. Draw the schematic for interfacing a stepper motor with 8051 microcontroller and
write 8051 ALP for changi g speed and direction of motor.
The complete board consists of tr nsformer, control circuit, keypad and stepper motor . The
circuit has inbuilt 5 V pow r supply so when it is connected with transformer it will give the
supply to circuit and motor both.
The 8 Key keypad is connected with circuit through which user can give the command to
control stepper motor. The control circuit includes micro controller 89C51, indicating LEDs,
and current driver chip ULN2003A. By giving different commands the stepper motor can run
clockwise, run anticlockwise, increase/decrease RPM,increase/decrease revolutions, stop
motor, change the mode, etc. Stepper motor has four coils.One end of each coil is tied
together and it gives common terminal which is always connected with positive terminal of
supply. The other ends of each coil are given for interface. Specificcolor code may also be
given.
First Coil L1-Orange

Second Coil L2 -Brown
Third Coil L3 - Yellow
Fourth Coil L4 - Black
Common Terminal -Red
By means of controlling a stepper motor operation we can
1. Increase or decrease the RPM (speed) of it
2. Increase or decrease number of revolutions of it
3. Change its direction means rotate it clockwise or anticlockwise
Fig:Interfacing of stepper motor with 8051 Microcontroller
To vary the RPM of motor we have to vary the PRF (Pulse Repetition Frequency).
Number of applied pulses will vary number of rotations and last to change
direction we have to change pulse sequence. So all these three things just depends
on applied pulses. Now there are three different modes to rotate this motor
1. Single coil excitation
2. Double coil excitation
3. Half step excitation
Pulses for stepper motor module
The circuit consists of very few compo e ts. The major components are 7805, 89C51
and ULN2003A.
Connections:-
1. The transformer terminals a e given to bridge rectifier to generate rectified DC.
2. It is filtered and given to r gulator IC 7805 to generate 5 V pure
DC. LED indicates supply is ON.
3. All the push button micro switches J1 to J8 are connected with port P1 as
shown to form serial keyboard
4. 12 MHz crystal is connected to oscillator terminals of 89C51 with two
biasing capacitors.
5. All the LEDs are connected to port P0 as shown
6. Port P2 drives stepper motor through current driver chip ULN2003A.
7. The common terminal of motor is connected to Vcc and rest all four
terminals are connected to port P2 pins in sequence through ULN chip.
4. Draw the schematic for interfacing a servo motor with 8051 microcontroller and write
for servo motor control. (Nov/Dec 2014)
Servo motors are self-contained mechanical devices that are used to control the
machines with machines. Usually the servo motor is used to control the angular motion among
from 0° to 180° and 0° to 90°. The servo motor working principle based on the PWM (pulse
width modulation) pulses.
A Servo motor is one of the most commonly used motor for precise angular movement.
The advantage of using a servo motor is that the angular position of the motor can be
controlled without any feedback mechanism.
Pulse Width Modulated (PWM) waves are used as co trol signals and the angular position is
definite by the width of the pulse at the control input. Servo motor having angle of rotation
from 0-180° and angular position can be controlled by varying the duty cycles among 1ms to
2ms.The control of s rvo motor connected port0 of 8051 microcontroller. The 11.0592MHz
crystal osc llator is used to provide the clock pulsed to the microcontroller and 22pf ceramic
capacitors used to stabilize the operation of crystal. 10KΩ and 10uf capacitor is used to
provide the power on reset to the microcontroller.
Controlling a Servo Motor with Angle rotations
Servo motor working principle mainly depends upon duty cycles. It uses Pulse Width
Modulated (PWM) aves as control signals. The angle of rotation is resolute by the pulse width
of the control pin.
Servo Motor Working Principle

The servo motor working principle mainly depends upon the „Fleming left hand rule‟.
Basically servo motors are adapted with DC motors, a position sensor, a Gear reduction, and
an electronic circuit. The DC motors achieve powered from a battery and run at high speed and
low torque. We assembled shaft and gear connected to DC motors then we can increase and
decrease the motor speed gradually.
Fig:Interfacing of servo motor with 8051 Microcontroller
The position sensor senses the location of the shaft from its fixed position and sends the
information to the control circuit. The control circuit decodes the signals accordingly from
the position sensor and compares the actual location of the motors with the preferred position
and accordingly controls the direction of rotation of the DC motor to get the necessary
position. Generally the servo motor requires 4.8V to 6 V DC supply.
5. Draw the schematic for interfacing a washing machine control with 8051
microcontroller and write8051 ALP for washing machine control. (Nov/Dec 2014) A
washing machine is an electronic device that is designed to wash laundry like clothes, sheets,
towels and other bedding. A washing machine is built with two steel tubs which are the inner
tub and the outer tub whose main role is to prevent water from spilling to other parts of the
machine.
Fig:Interfacing of washing machine with 8051 Microcontroller
Control knobs in ashing machine:

• Load select knob
• Water inlet select knob
• Mode select knob
• Program select knob
Load select knob:- load Number of clothes low medium high Load select
Water inlet select knob:- hot cold both-mixed Water inlet
Mode select knob:- Save mode Normal mode Mode
Program select knob:- Heavy Clothes very dirty Normal Normal dirty clothes LIGHT For
light dirty clothes Delicate For silk clothes
Machine Operations:-
 Fill:- water will be filled by the pump as per the load knob selected.
 Agitate:- The wash basket will rotate in a clockwise direction for 10 revolutions, After
that basket will stop for 2 seconds, then rotate 10 revolutions in anticlockwise direction.
The process will be continued for specified minutes in cycle table.Drain:- After agitation,
the water and detergent are drained.
 Spin:- During spin, agitator will be stationary, only the basket will rotate at high
speed. Then the moisture of clothes are removed through holes in the inner metallic
basket.
Machine Indicators:-
Machine ON
LED ON After completion of washing cycle, buzzer sound will be generated.
Washing cycle :
Heavy
Normal
Light
Delicate
Washing Machine Drives/Connections:

The drives of the washing machine is connected to 8051
Microcontroller ports.
Hot/Cold Agitator motor drive
Agitator motor drive
Spin motor drive
High level
Medium level
Low level
Drain
Washing machine ON LED
Heavy
Normal
Light
Delicate
Hot
Normal Buzzer sound Basket
Washing Machine Operation SinalsInput/Output :

The various Operation Signals are connected to microcontroller Input/output Port.
Load / water level select
Water inlet
Program select
Machine ON
Fill water
Agitation control
Output
Spin
Washing complete
Program:Commands for washing-machine controller
SETB LCALL JNB SJMP P2.0

FILL_1 P1.0,LOOP_1 HEAVY Machine ON indication Machine fill with water
1st time Chkprogsetng knob for heavy.
If P1.0 is not set,jump to LOOP_1
If P1.0 is set,jump to HEAVY LOOP_1 JNB SJMP P1.1,LOOP_2 NORMAL

Check progsetng knob for normal
If P1.1 is not set.jump to LOOP_2
If P1.1 is set, jump to NORM LOOP_2 JNB SJMP P1.2,LOOP_3 Chckprogsetng
knob for normal.
If P1.2 is not set,jump to LOOP_3
If P1.2 is set,jump to LIGHT LOOP_3 JNB SJMP P1.3,LOOP_4 DELICATE
Check prog set knob for delicate.
If P1.3is not set,jump to LOOP_4 If P1.2 is set,jump to delicate DISPLAY SETB
P2.7 Indicate the completion of wash cycle. LOOP 4 NOP LJMP 0000 End of
program

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Interrupts priority

9. Steps involved to fetch a byte in 8085?

i) The pc places the 16-bit memory address on the address bus

10. Define instruction cycle,machine cycle and T-state?

Instruction cycle is defined as the time required completing the execution of an

11.How many machine cycles does 8085 have, mention them?

14. Difference between memory mapped I/O and peripheral I/O ?

16-bit device address 8-bit device address

15. Define pipelining?

16. Discuss the function of instruction queue ?

. The basic units or blocks of a microprocessor are ALU, an array of registers

18. Explain the process control instructions

19. What happens to the 8085 processor when it is reset?

21.When the 8085 processor checks for an interrupt?

22. What is interrupt acknowledge cycle?

24.How the slow peripherals are interfaced with 8085 processor?

1.Draw and explain the architecture of 8085 in detail. (Nov/Dec-2013)

Figure: Architecture of 8085 Microprocessor

Arithmetic and Logic Unit (ALU):

Program Counter (PC):

Stack Pointer (SP):

Serial I/O Control:

Timing and Control unit :

ALE is used for provide control signal to synchronize the components of

Fig:Pin Diagram of 8085 Microprocessor

Address Bus:A8 - A15 (Input)

Multiplexed Address / Data Bus:AD0 - AD7 (Input/Output)

Control and Status signals:

ALE (output) - Address Latch Enable.

RD (output , active low) - Read

WR (output, active low) - Write

IO/M (output) - Memory/ IO

0 1 Memory Or I/O Write

1 0 Memory Or I/O Read

Interrupts and Externally initiated operations:

TRAP interrupt is a nonmaskable restart interrupt. It is unaffected by any mask or

Reset In (input, active low)

The program counter inside the microprocessor is set to zero.

Fig:Signal Diagram of 8085 Miicroprocessor

It indicates CPU is being eset.

SID (input) - Serial Input Data

SOD (output) - Serial Output Data

Direct Memory Access (DMA):

3.Explain the interrupt structure of 8085 microprocessor. (Nov/Dec-2013)

Interrupt is a signal s nd by an external device to the processor, to perform a

Interrupt Vector address

RST 7.5 003CH

RST 6.5 0034H

RST 5.5 002CH

MASKABLE & NON-MASKABLE INETRRUPTS:

Opcode Fetch Machine Cycle:

Memory Read machine cycle:

Memory Write Machine cycle:

IO read machine cycle:

Address decoding circuit using 3X8 decoder:

Types of address decoding:

2.What are the various types of 8085 instructions? MAY/JUNE2013,NOV/DEC2011

3. Explain the difference between a JMP instruction and CALL

4. What is meant by lookup table?NOV/DEC 2014

5. Explain the functioning of CMP instructions?NOV/DEC 2015

6. Mention the similarity and difference between compare and

8. What are the different types of addressing modes?NOV/DEC