23.What will be the status of the processor during bus idle cycle?

During bus idle cycle, the status signals S0 and S1 are both asserted low and data, address and
control pins are driven to high impedance state. Also, the processor will not sample the READY
signal.

24.How the slow peripherals are interfaced with 8085 processor?

The slow peripherals require longer read/write time than allowed by the processor. Hence to
interface slow peripherals, an extra hardware should be designed so that it introduces required
number of wait states in machine cycles between T1 and T2. An alternate solution is to interface
the slow peripherals using ports.

25.What is the difference between wait state and bus idle condition?

During bus idle condition, the tristate pins of the processor are driven to high impedance state, but
during wait state they are in normal states (either low or high). The READY is not sampled during
bus idle condition but it is sampled during wait state.

PART B

1.Draw and explain the architecture of 8085 in detail. (Nov/Dec-2013)

Address Bus:
The address bus is a group of 16 lines generally identified as A0 to A15. The address bus is
unidirectional and bits flow in one direction-from the MPU to peripheral devices.The MPU
uses the address bus to identify a peripheral or a memory (216 =
65,536) locations

Data Bus:

The data bus is a group of 8 lines used for data flow. These lines are bi-directional and data
flow in both directions between the MPU and memory and peripheral devices. The MPU
uses the data bus to transfer data.
Control Bus:
The control bus carries synchronization signals and providing timing signals.The MPU
generates specific control signals for every operation it performs.These signals are used to
identify a device type with which the MPU wants to communicate.
Registers of 8085:
The 8085 have six general-purpose registers to store 8-bit data dur ng program execution.
These registers are identified as B, C, D, E, H, and L.They can be combined as registerpairs-
BC, DE, and HL-to perform some 16-bit operations.