Design and Analysis of Odd- and Even-Parity

Generators and Checkers Using Quantum-dot

Cellular Automata (QCA)
Firdous Ahmad Peer Zahoor Ahmad G. Mohiud din Bhat
Department of Electronics & IT, Department of Computer Science, Department of Electronics & IT,
University of Kashmir, (J&K) University of Kashmir, (J&K) University of Kashmir, (J&K)
INDIA – 190006 INDIA -190006 INDIA – 190006
Email Id: firdousahmed15@[Link] Email Id: pzahoorcssc@[Link] Email Id: drgmbhat@[Link]

Abstract – Quantum-dot Cellular Automata (QCA) is an devices and implementing any logical function with QCA. In
emerging technology for nano-scale computing. There is an QCA signal is propagated by the position of charge and no
ever increasing demand for reliable data transmission over voltage or current flows between the cells. Computational
telecommunication networking systems. The researchers are power between QCA cells is provides by Coulombian
focusing on developing nano-devices that can detect/check interaction and power is not delivered to individual internal
errors during information communication. In this paper QCA cells [4]. The set of special rules including QCA design
novel 3-bit odd- and even-parity generators and checkers and timing rules for the development of efficient QCA is
using QCA nanotechnology, is presented. The proposed shown in [5-6]. Recent research have shown adder circuits in
techniques can be used to detect and check errors during QCA can achieve high density, fast switching speed, at room
information communication (message word). The parity temperature operations [7-9]. The logical AND, OR, NOT
generators and checkers have been designed based on QCA- gates including XOR/XNOR gates can be used for
XOR/XNOR gates. The circuits present a simple design using implementing any logical and functional circuits. However
homogenous layer of cells and effective technique to find XOR gate is an important component and has many
errors in data transmission systems. The results of computer applications in code converters [10] and pseudo-code
simulation tests carried on the proposed designs have generators [11].
confirmed the suitability of the proposed techniques. The main contribution of our paper is to design and simulate
QCADesigner tool, ver. 2.0.3, has been used for the the novel QCA odd parity generator and checker based on
simulations carried out in this paper. proposed XOR gate which can be used for reliable data
transmission in computers and communication networking
Keywords–Communication, Information, XOR/XNOR, Parity systems. In addition in this paper, our contribution is to
Generator, Parity Checker, QCA, Transmission. enhance the performance of proposed XOR gates including
even parity generator and checker which consists of less area,
I. INTRODUCTION clock delays and circuit complexity as compared to [12-15].
Moreover the proposed designs consume minimum number of
QCA has achieved a significant popularity in nano electronics
cell counts which maximizes the device density. A detailed
and became an interesting research option due to low power
comparison with regard to various characteristics is present in
consumption, high operating frequencies (T, Hz) and extremely
Table I. The proposed QCA circuits have been verified using
device dense structure for implementing any digital logic
exhaustive simulation for analyzing the defect that can occur
circuits. After decades of its final growth the minimum feature
during fabrication process.
in CMOS technology, is ultimately confronted with limitations.
For the last two decades researcher has focused on new devices
II. MATERIALS AND METHODS
that might replace conventional Complementary Metal Oxide
Semiconductor (CMOS) technology [1]. The basic unit of QCA device is a QCA cell with a set of four
According to ITRS report [2] summarizes several potential quantum dots positioned at the corners of a square shown in
solutions. QCA nanotechnology is a possible alternative at Fig. 1(a) [16-17]. The binary representation of QCA cell can
nano-scale. QCA was introduced in 1993 [3] and has gained be specified with its polarization. The polarization levels is
significant popularity by growing interest in computational shown in Fig. 1(b) are P= -1 (binary 0) and P=+1 (binary 1)

978-9-3805-4416-8/15/$31.00 2015
c IEEE 187
[18]. In QCA circuits no physical wire is used instead a grid (d) (e)
arrangement of QCA cells can be implemented as a wire [17]
shown in Fig. 1(c). For implementations of QCA circuits, basic
logic gates are required which are three-input majority gate and
inverter [19] shown in Fig. 1(d) and Fig. 1(e) respectively.
QCA AND gate and QCA OR gate is implemented by setting
one input (one of the three inputs of the majority gate) to a
fixed polarization. When a single input (any of the three inputs)
is set to 0, then the output is said to be AND gate of the other
two inputs. Moreover if a single input is set to 1, then the
output will be OR of the other two inputs. AND, OR and NOT
are the basic gates in QCA, using which any logical function
can be realized. (f)
The QCA clock is used to provide power gain and achieve
computational pipelining in QCA cells. Four clock zones are
used to control data flow direction in QCA circuits [20] shown
in Fig. 1(f). Each clock zone has four phases (Release, Relax,
Switch and Hold) and each phase lags by 900 with respect to
the previous clocking [21]. In QCA clock not only controls
data flow but also reduce power dissipation in QCA circuits.
Bennett clocking scheme should be used to provide better
power traces to remove the data dependence for different inputs
and making it impossible to perform power analysis attack (g) (h)
[20], [22].
The QCA devices can also be implemented by using both Fig. 1. (a) QCA cell with four quantum dots [16-17] (b) Two cell
coplanar crossing and multilayer crossing wire strategies that, polarizations [18] (c) QCA binary wire [17] (d) & (e) Majority gate and
Inverters [19] (f) The four QCA clock zones [20] (g) & (h) Coplanar and
is illustrated in Fig. 1(g) and (h). The coplanar cells has both Multilayer wire [23-25]
rotating and regular cells and have the inherent property to
cross two QCA wires to carry information without signal
interference, whereas multilayer QCA cells use different layers III. QCA IMPLEMENTATIONS
and stacked vertical cells to change layer.
A. QCA XOR Gates
The coplanar wire crossing scheme causes low robustness and
fabrication difficulties in QCA circuits [23]. However, XOR is usually two input digital logic gate which results true
multilayer crossing has fabrication difficulty due to (logic 1) output, when both the operands are not same. The
construction of multiple layers, but it is expected to perform output of XOR gate is false (logic 0) otherwise.
smooth operation, reliable data transmission and possible Fig. 2(a) shows the logic diagram of XOR gate and can
existence in QCA circuits [24-25]. Therefore, multilayer perform the logic function in general as:
scheme is an essential instrument on future QCA fabrication
technology. Y= .B+A. (1)

The schematic of majority XOR gates are shown in Fig. 2(b)

& (c) and can perform the majority logic function respectively
as:
(a) (b)

(2)

(3)

(c)

(a)

188 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom)
 (b)

(b)

(c)

Fig. 2. (a) Logic diagram of XOR gate (b) &(c) The schematic of QCA
majority XOR gates

The layout of XOR whose construction is based on Eq. 2 is

illustrated in Fig. 3(a). The simulation result of proposed XOR (c)
gate is shown in Fig. 3(b). The proposed XOR consists of less
area 0.03um2, circuit complexity of 30 cells & simulation result
is obtained after 3/4 clock delays, which is lesser than as
reported in [12-13]. The XOR gate shown in Fig. 3(a) is the
improved XOR gate of [10]. The XOR gate in [10] is not
working properly when used in complex circuits, therefore it
needs some corrections. However, XOR gate presented in [13]
is constructed in four layers and the layout presented in [12] is
constructed with rotating cells and consists of large area. The
multilayer design and large area causes low robustness and
fabrication difficulties in QCA circuits [22]. The second layout
of XOR whose constructed based on Eq. 3 is shown in Fig. 3(c)
consists of circuit complexity of 34 cells and area 0.04um2. The
second XOR gate explores the fact that the result is obtained (d)
after 1 clock delays and is shown in Fig. 3(d). It is also worth
noting that the new designs are denser than all the previous Fig. 3. (a) & (c) The QCA layout of XOR design (b) & (d) Simulation results
designs.
B. Parity Generators/Checkers
The parity bit generator is used in digital communications for
error detection and is transmitted in the form of 1’s and 0’s. A
parity generator is used at the transmitter to generate/append a
parity bit with the message word. The message word including
the parity bit is transmitted and then checked at the receiving
end for errors. An error is detected if the checked parity does
not correspond with the one transmitted.
An even parity bit generates an output 0 if the number of 1’s
in the input sequence is even and 1 if the number of 1’s in the
input sequence is odd. The even parity checker gives an output
0, if there is no error in the parity bit generated.
(a)

2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom) 189
While in odd parity bit generates an output 1 if the number 1’s
in the input sequence is even and 0 if the number of 1’s in the
input sequence is odd. The odd parity checker gives an output 1
if there is no error in the parity bit generated.
Thus, in both cases even/odd parity checkers it checks to see if
the parity bit generated is error free or not.

C. The Proposed Odd Parity Generator

Fig. 4(a) shows the logic diagram of odd parity generator. By
concatenating the parity bit to the message word, a transmitted
bit pattern will be formed which has an odd number of 1’s (i.e.
odd parity). If the received four bits has even number of 1’s an
error will occur during the transmission, indicating that one bit
has changed during transmission. (d)
Eq.4 is obtained from Truth table shown in Fig. 4(b) and can
expressed as: Fig. 4. (a) Logic diagram of odd parity generator (b) Truth table (c) The layout
of odd parity generator (d) Simulation results
P = Ȉ (0, 3, 5, 6) (4)
The logic expression for Eq. 4 can be represented as:
P = A'B'C' + A'BC + AB'C + ABC'= (A B C)' (5) D. The Proposed Odd Parity Checker
The layout of proposed odd parity generator whose The logic diagram of 4-bit odd parity checker is shown in Fig.
construction is based on Eq. 5 is shown in Fig. 4(c). Fig. 4(d) 5(a). In this A, B, C represents the three input message bits
depicts the simulation result of the proposed design. The circuit and ‘P’ is the parity bit. The four received bit (included three
is implemented with homogeneous layer of 900 cells, with fever message bits) is applied to the parity checker at receiver. Since
crossovers. The circuit consists of 1.75 clock delays, area 0.09 odd parity checker is used the receiver computes the parity
um2 and circuit complexity of 66 cells. from the three message bits and compares it with the received
parity bit ‘P’. If the computed and the received parity bits are
same, then no error has occurred.
Eq. 6 is obtained from Truth table shown in Fig. 5(b) and can
expressed as:
Check = Ȉ (0, 3, 5, 6, 9, 10, 12, 15) (6)

The logic expression for Eq. 6 can be represented
as:
(a) (b)
Check = A'B'C'P' + ABC'P' + A'BC'P + A’BCP’+AB'CP'+

AB'C'P+ABC'P'+ABCP= (A B C P)' (7)

The QCA layout of proposed parity checker is shown in Fig.
5(c). The Circuit complexity of the proposed circuit is 94 cells
and its area is 0.13um2. The simulation result is obtained after
an interval of 1.75 clock cycles as shown in Fig. 5(d).

Another design of odd parity checker shown in Fig. 5(e) with

XNOR gates contains circuit complexity of 94 cells, area 0.13
um2, and latency 1.75 clock delays. The simulation results of
XNOR parity checker is shown in Fig. 5(f).

(c)

190 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom)
(a) (b) (e)

(f)

Fig. 5. (a) Logic diagram of odd parity generator (b) Truth table (c) The
layout of proposed odd parity checker (d) Simulation results (e) Another
(c)
design of odd parity checker using XNOR gates (f) Simulation results of
XNOR parity checker

E. The Proposed Even Parity Generator

The logic diagram of even parity generator & Truth table is
shown in Fig. 6(a) & (b). Similarly in even parity generator by
concatenating the parity bit to the message word, a transmitted
bit pattern will be formed which always has an even number
of 1’s (i.e. has even parity).
The proposed parity generator is shown in Fig. 6(c), which has
less circuit complexity of 64 cells, area 0.09 um2 and latency
2.75 clock delays. The simulation result of parity bit ‘P’ is
shown in Fig. 6(d). The performance of propose design is
(d) present in Table II and has compared with [14-15] which is
present in Table I.
Eq.8 is obtained from Truth table shown in Fig. 6(b) and can
expressed as:

P = Ȉ (1, 2, 4, 7) (8)

The logic expression for Eq. 8 can be represented

as:

2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom) 191
P = A' B' C + A' B C' + A B' C' +A B C The logic expression for Eq. 10 can be represented
= (A B C). (9) as:
Check = A'B'C'P + A'B'CP + A'BC'P' + A'BCP+AB'C'P'
+AB'CP+ ABC'P+ABCP' = (A B C P) (11)
The QCA layout of even parity checker is shown in Fig. 7(c),
which consists less circuit complexity 94 cells, area 0.11 um2,
and latency 1.75 clock delays. Fig. 7(d) depicts the simulation
result of proposed parity checker.

(a) (b)

(a) (b)

(c)

(c)

(d)

Fig. 6. (a) Logic diagram of even parity generator (b) Truth table (c) The layout
of even parity generator (d) Simulation results

F. The Proposed Even Parity Checker

Similarly, as in case of parity checker for odd parity, the logic

diagram of the 4-bit even parity checker is shown in Fig. 7(a)
and Truth table Fig. 7(b).
Eq.10 is obtained from Truth table shown in Fig. 7(b) and can (d)
expressed as:
Fig. 7. (a) Logic diagram of even parity checker (b) Truth table (c) The layout
of even parity checker (d) Simulation results.
Check = Ȉ (1, 2, 4, 7, 8, 11, 13, 14). (10)

192 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom)
 TABLE I. CONVENTIONAL TABLE

CONVENTIONAL FEATURE TABLE

Featur XOR design Even Parity Generator/Checker design
es
[12] [13] PG [14] PC [14] PG [15] PC [15]
Compl
exity
45 49 99 145 60 117
(No of
cells)
Area
0.05 0.066 0.17 0.28 0.052488 0.135432
(um2)
Latenc
y
1 1 2 3 2 2.25
(clock
delay) (a) (b)
* Parity Generator (PG) and Parity Checker (PC).

Fig. 8. (a) Circuit complexity and area occupied (b) Latency (clock delays)
TABLE II. PROPOSED TABLE and area occupied.

PROPOSED FEATURE TABLE V. CONCLUSION

Odd & Even Parity Generator/Checker In this research work, we have design the novel
Features XOR design
design
Fig. Fig. Fig. Fig. Fig. Fig. Fig.
implementations of odd and even parity generators and
3(a) 3(c) 4(c) 5(c) 5(e) 6(c) 7(c) checkers with several adventages of circuit parameters. The
Complex proposed parity generators and checkers can be effectively
it (No of 30 34 66 94 94 64 94 used for error detection and check for reliable data
cells)
transmission in telecommunication networks. The XOR gates
Area
(um2)
0.03 0.04 0.09 0.13 0.13 0.09 0.11 and even parity generator/checker presented in this work has
compared with the several designs available in the literarure. It
Latency
(clock 0.75 1 1.75 1.75 1.75 2.75 1.75
has shown that the proposed design have significent
delay) adventages, with regards to various circuit parameters like
* Parity Generator (PG) and Parity Checker (PC). area, circuit complexy and clock delays. It is pertinent to
mention that the authors have not found any QCA design for
IV. COMPARISON odd parity generator/checkers in available literature for
comparison. The design and simulation results of present work
In this section, we have compared the proposed QCA XOR
have varified using QCADesigner tool.
gates and its novel implementation of odd and even parity
generator and checkers corresponding to conventional designs
ACKNOWLEDGEMENT
with regards to clock delays, area, and complexity (No. of
cells). The efficiency and compact size of the proposed designs One of the authors is highly thankful to UGC, India for
have been established as a result of comparison and is shown in providing Dr. D.S. Kothari UGC-PDF for carrying out this
Table I & Table II. work. We are also thankful to Prof. Javid Ahmad of
Table II outlines the comparison between the QCA XOR gates Electronics and Instrumentation Department for help and
and even parity generator/checker presented in the paper and necessary discussions.
those proposed in literature [12-15] which is present in Table I. REFERENCES
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194 2015 2nd International Conference on Computing for Sustainable Global Development (INDIACom)