USING QCA TECHNOLOGY TO

DESIGN NANO CIRCUIT LIBRARIES

FOR VLSI CIRCUITS
Presentation by:
Mr. C. LAXMIKANTH REDDY
Enrollment No.: SSSEC1620W

Subject: ELECTRONICS & COMMUNICATION ENGINEERING

Supervisor:
DR. ANIL KUMAR

Sri Satya Sai University of Technology & Medical

Sciences, Sehore – M.P.
 INTRODUCTION
 In the last two decades, contemporary Complementary Metal
Oxide Semiconductor (CMOS) circuits dominated the Integrated
Circuit (IC) technology in a rapid manner. However, CMOS
circuits suffer from short channel effects and quantum effects,
which limit the IC technology to progress further in
Nanotechnology devices design.
To overcome these CMOS limitations, a new technology
named Quantum-dot Cellular Automata (QCA) is introduced
in the nano device design
Even though, many efficient arithmetic circuits are designed
using QCA; still, there is a lot of improvement required to fulfill
the design requirements of the nano circuit Structures.
The proposed design methodology improves the speed of
The circuit and minimizes the circuit area significantly
 LITERATURE REVIEW
• Chabi, Amir & Roohi (2016) A tale XOR gate and furthermore
another way to deal with actualize 2:1 multiplexer are introduced.
Also, an effective and strong general reversible gate dependent on
the proposed XOR gate is designed.

• Sofeoul-Al-Mamun, (2017). In this paper, a 8-3 encoder circuit is

proposed dependent on QCA logic gates: the 4-input Majority
Voter (MV) OR gate. This 4-input gate can be designed into
numerous helpful gate structures, for example, a 4-info AND gate,
a 4-info OR gate.

• Kassa, Sankit & Karthik (2018) Quantum dot cellular automata

(QCA) are the most forthcoming technology which can supplant
CMOS technology with numerous extraordinary highlights that
can conquer all the constraints in CMOS. QCA is of fast, little
size and of low power utilization meeting all the features of nano
technologies and is more powerful than CMOS.
OBJECTIVES
• To study the QCA technology to design nano circuit
libraries for VLSI circuits.

• To analyze the single layer structure of XOR gate, serial bit

stream cascading magnitude comparator and its results

• To analyze the implementation of single-digit BCD adders

for ESDBA and HSDBA layout design

• To determine the result of high-speed optimization multi-

digit BCD adders for EMDBA N-digit and HMDBA

• To study the CMOS as fine as to put up the digital circuits at

nano-scale.
Quantum –Dot Cell

Majority Gate
RESEARCH METHODOLOGY
Single layer structure of XOR gate: A logic gate is an electronic
switch, which implements Boolean logic functions to produce a
one output dependent on one or more binary inputs. The design
of logic gates is significant in the development of logic circuits,
and it plays a key role in the digital processing arithmetic unit.

Apart from the fundamental logic gates AND, OR, NOT,

universal gates (NAND and NOR), the XOR gate has a particular
capability and has numerous applications.

The XOR gate is especially helpful in computational tasks, VLSI

testing (Linear Feedback Shift Register (LFSR) in Built-In Self-
Test (BIST) models) and correspondence based circuit
applications for blunder discovery and adjustment circuits like
Parity generator and checker, and so forth
Enhanced XOR gate schematic and Layout Diagrams

Half – adder schematic and Layout Diagrams

FULL - ADDER
LOGIC DIAGRAM OF PROPOSED EVEN PARITY GENERATOR

LOGIC DIAGRAM OF PROPOSED PARITY CHECKER

EQUALITY COMPARATOR
ENHANCED X-OR GATE SIMULATION RESULT
HALF ADDER SIMULATION RESULTS
ODD PARITY GENERATOR – SIMULATION RESULTS
COMPARISON OF ENHANCED GATE STRUCTURE WITH EXISTING X-OR
HALF ADDER

FULL ADDER
PARITY GENERATOR

EQUALITY BYTE COMPARATOR

MAGNITUDE COMPARATOR
PROPOSED 4- BIT MAGNITUDE COMPARATOR – SIMULATION RESULT
SHEMATIC DIAGRAM AND SIMULATION RESULTS OF
PROPOSED SINGLE DIGIT BCD ADDER (SDBA)
BLOCK DIAGRAM OF PROPOSED ESDBA
PROPOSED HMDBA
CONCLUSION
• In this part, we introduced an enhanced XOR gate structure and its
applications. The uses of XOR gate structure, for example, Half Adder,
Full Adder, Equality Byte Comparator, Parity Generator, and Checker
are introduced. The proposed circuit formats are straightforward in
structure with the most un-conceivable number of cells and with less
deferral. In this section, the proposed engineering XOR gate is executed
in a solitary layer structure as opposed to utilizing the hybrids and
accomplished huge improvement in execution. The presentation
correlation of various usages of XOR gates developed utilizing QCA is
clarified in detail. It is discovered that all the proposed designs are
significantly improving the exhibition results contrasted with the current
strategies. The introduced format designs can be productively used to
understand the other complex circuits.
• An epic design of falling sequential piece stream extent comparator is
introduced. This epic methodology sequential circuit is simply a
combinational circuit, which successfully uses the adiabatic clocking of
QCA. Proposed new sequential falling comparator QCA circuit
improves speed and lessens the multifaceted nature contrasted with past
• The ESDBA design is implemented with area efficient binary adder
using generate and propagate functions and introduces a new
correction logic to anticipate the ripple carry propagation in the
upper part of the existing BCD adder. The ESDBA offers the best
trade-off among area-delay of CFA and CLA-based BCD adders.
• The proposed HMDBA design is significantly faster compared to
CFA-based BCD adder and utilized less number of cells compared to
the CLA-based BCD adder.
• The proposed HMDBA and EMDBA designs are effective contrasted
with all the current designs.
• In this proposal, the usage of streamlined logic circuits utilizing QCA
is clarified in detail. All the proposed circuits were assessed utilizing
different boundaries, for example, various cells (cell check), region,
inertness, and clock zones and introduced the exhibition of the
proposed designs were effective contrasted with the current strategies
in QCA.
FUTURE SCOPE
• The major performance parameters such as the number of
cells, area and clock cycles provide further future work
improvements of efficient digital circuits to implement
using QCA.
• In future QCA will have a broad spotlight on strategies
for proficient routing and interconnect. Apart from that,
the future work in the zone of QCA framework
computerization will fixate the system, to characterize
timing zones.
• For future adaptations of the QCADesigner, incorporating
an outline standard with various design capacities such as
accurate power, energy estimation, and more precise
timing models improve the capability of QCA technology
to reproduce the efficient digital circuits.
 REFERENCES
• Vijay Kumar Sharma.(2020). Optimal design for digital comparator
using QCA nanotechnology with energy estimation.
International Journal of Numerical Modelling: Electronic Networks,
Devices and Fields
Early View. https://doi.org/10.1002/jnm.2822.

• Bilal, Bisma & Ahmed, Suhaib & Kakkar, V.. (2018). Quantum dot
cellular automata: A new paradigm for digital design. International
Journal of Nanoelectronics and Materials. 11. 87-98.

• Bilal, Bisma & Ahmed, Suhaib & Kakkar, Vipan. (2017). QCA
Based Efficient Toffoli Gate Design and Implementation for
Nanotechnology Applications. International Journal of Engineering
and Technology. 9. 84-92. 10.21817/ijet/2017/v9i3/170903S015

• Das, Jadav & De, Debashis. (2016). Optimized Design of Reversible

Gates in Quantum Dot-Cellular Automata: A Review. Reviews in