E cient designs of QCA Full-adder and 4-bit QCA

RCA Circuits
Sang-Woong Lee
Gachon University
Amir Masoud Rahmani
National Yunlin University of Science and Technology
Nemat Azimi
Islamic Azad University
Behrouz Safaiezadeh
Islamic Azad University
Mehdi Hosseinzadeh

Duy Tan University

Research Article

Keywords: Ripple Carry Adder, Full-Adder, Coplanar, Nanotechnology, QCA

Posted Date: March 7th, 2024

DOI: https://doi.org/10.21203/rs.3.rs-4010758/v1

License:   This work is licensed under a Creative Commons Attribution 4.0 International License.
Read Full License

Additional Declarations: No competing interests reported.

 Efficient designs of QCA Full-adder and 4-bit QCA RCA Circuits
Sang-Woong Lee1, Amir Masoud Rahmani2, Nemat Azimi3, Behrouz Safaiezadeh4, and Mehdi Hosseinzadeh5, 6, *
1 Pattern Recognition and Machine Learning Lab, Gachon University, 1342, Seongnamdaero, Sujeonggu, Seongnam
13120, Republic of Korea

2
Future Technology Research Center, National Yunlin University of Science and Technology, Yunlin, Taiwan

3
Young Researchers and Elite Club, Khoy Branch, Islamic Azad University, Khoy, Iran
4
Department of Computer, Andimeshk Branch, Islamic Azad University, Andimeshk, Iran
5 Institute of Research and Development, Duy Tan University, Da Nang, Vietnam.

6 School of Medicine and Pharmacy, Duy Tan University, Da Nang, Vietnam

* Corresponding author: Mehdi Hosseinzadeh (mehdihosseinzadeh@duytan.edu.vn).

Abstract: Quantum-dot Cellular Automata (QCA) technology offers several advantages

over traditional CMOS technology, including reduced power consumption, higher clock
speeds, and increased density. QCA has the potential to overcome the physical
limitations of CMOS, making it an attractive choice for the future of VLSI circuits. It uses
quantum dots to represent binary information. Digital arithmetic operations are
performed by adder circuits. A Ripple Carry Adder (RCA) is a digital circuit used in
digital electronics to add multiple binary numbers together. In QCA technology, the
implementation of such adders is notably different from traditional CMOS-based
implementations due to the unique properties and principles of QCA. It is constructed
by interconnecting a series of Full-adders. In this study, we introduce a high-performance
single-bit Full-adder as well as 4-bit RCA circuit developed using QCA technology. Our
proposed designs are simulated using QCADesigner 2.0.3 in a coplanar crossover way.
Our 4-bit RCA design outperforms existing designs by achieving a remarkable 23%
reduction in cell counts, 66% and 90% decrease in latency and circuit costs. Furthermore,
power dissipation metrics for our single-bit Full-adder were ascertained using the
QCAPro tool, with findings showing over 40% energy savings relative to the best current
designs.

Keywords: Ripple Carry Adder, Full-Adder, Coplanar, Nanotechnology, QCA

1. Introduction

The Complementary Metal-Oxide-Semiconductor (CMOS) technology is used to

develop digital logic circuits. But this technology has recently faced challenges and
drawbacks such as high temperature, leakage current, and ultra-low power. Therefore,

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numerous studies have been done to identify a good substitute for this technology.
Quantum-dot Cellular Automata (QCA) technology is introduced as a new technique at
nanoscale to replace the CMOS technology [1]. This technology offers several advantages
over traditional CMOS for VLSI circuits. It provides higher integration densities, lower
power consumption, and potentially faster processing speeds due to the utilization of
quantum properties. These advancements make QCA a promising solution to address
the inherent limitations of CMOS technology [2]. They use quantum effects rather than
electric current to perform operations in this technology. The core element of this
technology is the QCA cell. Each cell has a square structure that includes four dots in its
corners. Two electrons move freely between these dots. Due of the electrostatic repulsion
between these electrons, electrons tend to reside in diameter square. Many different
structures have been suggested to carry out addition operations, and has advantages and
disadvantages in comparison to other designs. This paper has two new ideas. The first
idea is to design a Full-adder in QCA technology. The second idea is to design a 4-bit
RCA using the presented Full-adder in QCA technology. The QCADesigner 2.0.3 tool is
utilized to simulate these two designs [3]. The result of simulation demonstrates that the
presented structure outperforms all earlier designs based on latency, cell counts, and
occupied area. The main contributions of the suggested RCA and Full-adder circuits are:

• Reducing the number of cells compared to previous designs

• Decreasing the occupied area compared to previous designs
• Decreasing the complexity circuit compared to previous designs
• Calculating the power dissipation of the suggested Full-adder layout
The remainder of the paper is structured as follows: In the second section, the
summary of QCA technology is presented. In the third section, the previously proposed
Full-adders and RCAs are review. In Section fourth, design of the proposed Full-adder
circuit and 4-bit RCA are discussed. In the section fifth, simulation and comparison of the
suggested designs are discussed. The power dissipation of the suggested single-bit Full-
adder is calculated in section 6. In the end, conclusion is presented.
2. Summary of QCA

This section provides fundamental concepts of QCA technology include logic gates,
wire, and clocking. Logic gates are the basic building blocks to perform logical and
arithmetic operations. These logic gates are interconnected to create complex circuits for
performing more advanced computations. Clocking is also an essential concept, as it
ensures that the signals propagate correctly throughout the QCA circuits. Understanding
these concepts is crucial for understanding the functioning and design of QCA
technology. Each QCA cell consists of four quantum dots positioned at its corners. These

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four quantum dots in each QCA cell are used to store and process quantum information.
This arrangement allows for manipulation of the quantum states of the dots, which can
be used for information processing and quantum computing applications [4]. There are
also two electrons in each cell that move freely between these dots. The electrons occupy
diagonal positions against one another due to Coulomb repulsion. The diagonal
arrangement of electrons in a cell is a consequence the Coulomb repulsion between
electrons with same charges. This arrangement allows for the maximum spacing between
electrons and helps to stabilize the overall structure of the atom. This property creates
two completely stable states, which are expressed as cellular polarization P = −1 (logic
“0”) and P = +1 (logic “1”), as shown in Fig 1.

Quantom-dot

P = -1 P = +1

Logic Logic

Electron

Fig 1. QCA cell

In QCA, the basic structures known as inverter and majority gates are used for
designing logic circuits. The majority gate in QCA performs logic takes multiple inputs
and outputs a signal based on the majority of those inputs, as shown in Fig 2a. If the
majority of inputs are high, it produces a high output signal; if the majority of inputs are
low, it produces a low output signal. The inverter gate acts as a NOT gate. An example
of the design of this structure can be seen in QCA, as shown in Fig 2b. By combining and
arranging these gates in different configurations, complex logic functions can be
implemented using QCA. AND gate and OR gate are basic logic gates used in digital
electronics. An AND gate outputs a high signal (logic 1) only when all of its inputs are
high, otherwise it outputs a low signal (logic 0), as shown in Fig 2c. On the other hand,
an OR gate outputs a high signal if any of its inputs are high, and only outputs a low
signal if all of its inputs are low, as shown in Fig 2d. These gates are widely used in digital
circuits to perform logical operations. The QCA wire is constructed by arranging the QCA
cells in a linear formation, either in a row or a column. This enables the transmission of
signals and the processing of information through the QCA system [5].

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 Fig 2. The QCA structure a) Majority b) Inverter c) AND d) OR

There are techniques known as single-layer, multi-layer and logical for wire crossing
in the simulation and design of a QCA circuit:

• Single-layer: This approach uses 45° and 90° cells at the intersection

• Multi-layer: This method uses several layers at the intersection of the wires.

• Logical Crossing: This method also uses one layer in the design, with the difference
that it uses cells with two clock differences at the intersection [1].

The clocking mechanism is an additional concept employed to design circuits with QCA.
It is a crucial component in designing circuits with QCA. It is responsible for controlling
the operation of the circuit and ensuring that the interactions between cells occur in a
synchronized manner. By using clock signals, the timing of the circuit can be precisely
regulated, allowing for reliable and accurate computations [6]. In QCA circuits four clock
signals with 90° phase difference is typically used, namely switch, hold, release, and relax
[7]. In QCA circuits, the clock signals serve as timing references for controlling the
behavior of the QCA cells. The switch clock signal initiates the switching of the cells, the
hold clock signal maintains the state of the cells, the release clock signal allows for the
release of the previous cell state, and the relax clock signal prepares the cells for the next
computation. The 90° phase difference between these clock signals ensures the proper
sequencing and synchronization of the QCA circuit, enabling efficient and accurate
computation.

3. State of the arts Full-adders and RCA

The introduction of various Full-adder and RCA circuits using QCA technology in
recent years reflects a growing focus on optimizing evaluation criteria such as circuit cost,
delay, power usage, cell numbers, and the circuit's area. These developments are aimed
at improving the efficiency and performance of circuits in QCA technology, allowing for
more efficient and effective circuit designs. Scholars have introduced diverse Full-adder

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and RCA circuits using QCA technology. Here, we'll overview a few notable QCA-
implemented Full-adders and RCA circuits. Vahabi et. al. [8] proposed two novel Full-
adders and then simulated two new RCA circuits in QCA technology. Their Full-adder
design utilized 35 cells and occupied a space of 0.027 𝜇𝑚2 . It also had a 0.5 clock cycles
delay, indicating the time it takes for a complete operation to be executed. Their 4-bit
RCA design included 209 cells, spanned an area of 0.25 𝜇𝑚2, and had a 1.25 clock cycles
delay. Mohammadi et. al. [9] introduced a novel Full-adder and a 4-bit RCA circuit in
QCA technology. The QCA layout of suggested Full-adder had 38 cells, consumed an
area of 0.02 𝜇𝑚2, and had a latency of 0.75 clock cycles. The QCA layout of presented 4-
bit RCA circuit contained 237 cells, covered an area of 0.24 𝜇𝑚2, and delay of 1.5 clock
cycles. Notably, these designs were simulated across three layers. Gassoumi et. al. [10]
designed and simulated a Full-adder that included 45 cells, an area of 0.04 𝜇𝑚2, and a
latency of 0.5 clock cycles in QCA technology. Abedi et. al. [11] designed and simulated
a Full-adder consists of 59 cells, occupying an area of 0.04 𝜇𝑚2 , and one clock cycles
latency in QCA technology. This design consists of three majority gates and a pair of
inverter gates. This structure was simulated in coplanar crossover way. Seyedi et. al. [12]
suggested a 4-bit RCA circuit in QCA technology. The QCA layout of suggested 4-bit
RCA circuit contained 89 cells, covered an area of 0.12 𝜇𝑚2, and delay of 3.75 clock cycles.

4. The Suggested Structures

The new structures for single-bit Full-adder and 4-bit RCA circuits in QCA are
explained in detail in this section. This includes the arrangement of the cells, input and
output configurations, and the overall functioning of the circuits. The purpose of these
structures is to improve the performance and efficiency of QCA circuits, taking into
account the constraints and advantages of QCA technology.

4.1 The Suggested Single-bit Full-adder

An addition operator is a key mathematical operator. In order to implement other

operators like multiplication, division, and subtraction uses addition operator.
Considering the importance of this operator, it can be concluded that if the adder logic
circuit is designed in the best possible way, it effectively optimizes the performance of
the computing circuit. A single-bit Full-adder is a logical circuit that receives three values
(two inputs (bits) and a Carry-in bit) as input and produces two outputs consists of sum
bit and the Carry-out bit. The suggested Full-adder circuit includes three inputs of 𝐴, 𝐵,

5
and Carry-in (𝐶𝑖𝑛 ) and two outputs of sum (𝑆), and Carry-out (𝐶𝑜𝑢𝑡 ). The value of 𝑆, and
𝐶𝑜𝑢𝑡 is calculated based on relations (1) and (2). Fig 3 displays the block diagram of the
single-bit Full-adder.
𝑺 = 𝑴𝒂𝒋𝒐𝒓𝒊𝒕𝒚 (𝑨, 𝑩, 𝑪𝒊𝒏 ) = 𝑨𝑩 + 𝑨𝑪𝒊𝒏 + 𝑩𝑪𝒊𝒏 (𝟏)

𝑪𝒐𝒖𝒕 = 𝑿𝑶𝑹 (𝑨, 𝑩, 𝑪𝒊𝒏 ) = 𝑨 ⊕ 𝑩⨁ 𝑪𝒊𝒏 (𝟐)

Fig 3. The diagram block of suggested single-bit Full-adder

4.2 The Suggested RCA Circuit

The RCA stands as the most basic form of an adder. RCA is a fundamental digital
circuit used in digital electronics to add multiple binary numbers together. In traditional
CMOS-based implementations, the RCA consists of logic gates like AND, OR, and XOR
gates arranged in a particular configuration. An N-bit RCA circuit involves linking N
Full-adders so that 𝐶𝑜𝑢𝑡 of the previous Full-adder is used as 𝐶𝑖𝑛 of the next one. The
proposed 4-bit RCA performs the addition of two four-bit binary numbers. Therefore, in
the proposed design, we need four single-bit Full-adders, where 𝐶𝑜𝑢𝑡 of each full adder
is connected to 𝐶𝑖𝑛 of the next one. Fig 4 shows the block diagram of the proposed 4-bit
RCA. In this design, 𝐴𝑖 is the i-th bit of input 𝐴, 𝐵𝑖 is also the i-th bit of input 𝐵, and 𝐶𝑖−1
is the Carry-in of the i-th Full-adder. 𝑆𝑖 and 𝐶𝑖 are the Least Significant Bit (LSB) and the
Most Significant Bit (MSB) of each Full-adder after the addition operation, respectively,
which are calculated based on the relations (3) and (4):
𝑺𝒊 = 𝑴𝒂𝒋𝒐𝒓𝒊𝒕𝒚 (𝑨𝒊 , 𝑩𝒊 , 𝑪𝒊−𝟏 ) = 𝑨𝒊 𝑩𝒊 + 𝑨𝒊 𝑪𝒊 + 𝑩𝒊 𝑪𝒊−𝟏 (𝟑)

𝑪𝒊 = 𝑿𝑶𝑹 (𝑨𝒊 , 𝑩𝒊 , 𝑪𝒊−𝟏 ) = 𝑨𝒊 ⊕ 𝑩𝒊 ⨁ 𝑪𝒊−𝟏 (𝟒)

6
 Fig 4. The presented diagram of 4-bit RCA

5. Simulation and comparison of results

QCADesigner [3] is a useful tool for simulating proposed designs. It helps us test and
evaluate the designs before implementation, ensuring that they meet the necessary
requirements and perform as intended. By using QCADesigner, we can identify any
potential issues or areas for improvement early on, ultimately saving time and resources
in the design process. We use QCADesigner tool to simulate the proposed designs. The
reminder of this section shows simulation of the proposed designs described in sections
4.1 and 4.2 in QCA technology. Also, we compare the suggested single-bit Full-adder and
4-bit QCA RCA with prior works.

5.1 Simulation of suggested single-bit Full-adder

Fig 5 presents a visual representation of a Full-adder circuit simulated using QCA

technology. It likely demonstrates the functionality and performance of the proposed
Full-adder design in QCA. The proposed design showcases a high level of innovation,
particularly in the arrangement of cells for optimal design and use in digital parts.
Notably, all inputs are positioned outside the design, ensuring that they are not enclosed
by other cells. This feature enhances the ease and convenience of incorporating this
design in other digital parts. The suggested Full-adder has a relatively small number of
cells (13) and a compact occupied area (0.01 𝜇𝑚2 ) which suggests it could be implemented
efficiently in integrated circuits. Additionally, its latency of 0.5 clock cycles indicates that
it can perform addition operations within a reasonable amount of time. Overall, the
suggested Full-adder offers efficient performance in terms of size and speed. Relation (5)
[13] is used to calculate the cost of the circuit, which is equal to 0.0025.
𝑪𝒐𝒔𝒕 = 𝒂𝒓𝒆𝒂 ∗ 𝒍𝒂𝒕𝒆𝒏𝒄𝒚𝟐 (𝟓)

7
 Fig 5. Single-bit QCA Full-adder circuit

5.2 The Result of simulation of the suggested Full-adder

Simulation result of the suggested Full-adder block is shown in Fig 6. The inputs of
Full-adder are 𝐴, 𝐵 and 𝐶𝑖𝑛. The outputs of the circuit are 𝑆 and 𝐶𝑜𝑢𝑡 respectively. The
MSB and the LSB of the output are 𝑆 and 𝐶𝑜𝑢𝑡. It provides insight into how the Full-adder
operates and produces the expected output based on these inputs. The result of
simulation confirms that the circuit is functioning accurately and producing the expected
output.

Fig 6. The result of simulation of the suggested single-bit QCA Full-adder

8
5.3 Suggested 4-bit RCA

Fig 7 depicts the simulation of the suggested 4-bit QCA RCA circuit. In the
simulation of the suggested 4-bit QCA RCA circuit, four inverters (INVs) and four QCA
XOR gates are employed. It employs inverters and XOR gates to perform the addition
operation. XOR gates are fundamental logic gates that produce a true output when the
number of true inputs is odd. They are crucial in performing binary addition because
they generate the sum bit for each stage of the adder. In a 4-bit RCA, XOR gates are used
to calculate the sum of each bit position while considering the carry from the previous bit
position. Inverters are used to invert the logical state of a signal. They help in
manipulating and controlling the flow of information within the circuit. By simulating
the circuit, designers can analyze its performance characteristics, such as speed and
correctness of operation. The carry-out from each stage becomes the carry-in for the next
stage, allowing for the propagation of carry across multiple bits. The design encompasses
68 cells, occupies an area of 0.1 𝜇𝑚2 , and provides results with a delay of 1.25 clock cycles.
In terms of cost, the circuit is valued at 0.1562. The small number of cells in the proposed
design indicates that it is less complex and more compact. Additionally, the low delay of
the circuit suggests that it has a faster speed compared to other designs.

Fig 7. Simulation of suggested 4-bit QCA RCA circuit

5.4 The result of simulation of the suggested 4-bit RCA

Fig 8 depicts the simulation waveforms of suggested 4-bit QCA RCA. As seen in
Figure 8, if the input value 𝐴(3: 0) = 15 and the input value 𝐵(3: 0) = 15, and 𝐶𝑖𝑛 = 1, the
output S (3:0) after a delay of 1.25 clock cycles is 31. It shows 𝐶𝑜𝑢𝑡 = 1. Also, if the input

9
value 𝐴(3: 0) = 2 and the input value 𝐵(3: 0) = 10, and 𝐶𝑖𝑛 = 1, the output S (3:0) after a
delay of five zones clock is 13. It shows that 𝐶𝑜𝑢𝑡 = 0.

Fig 8. The simulation waveforms of suggested 4-bit RCA in QCA

5.5 Comparison of the previous Full-adders with the proposed scheme

In this section, we compare our single-bit Full-adder against some of the most
recent standout designs. As shown in Table 1, the evaluation metrics are: circuit cost,
delay, cell count, the total area occupied, and the kind of crossover. Table 1 compares the
proposed Full-adder versus various designs. The proposed Full-adder design has
considerable advantages compared to previous designs in terms of its evaluation
parameters, including fewer cells, reduced delay, minimized space consumption, and
lower circuit cost or complexity. Specifically, the number of cells, latency, and cost of the
suggested single-bit Full-adder are reduced by about %35, %33, and %72 compared to the
QCA Full-adder in [12]. The small number of cells in the proposed design indicates that
it is less complex and more compact, which can be beneficial in terms of cost, space, and
energy efficiency. Additionally, the low delay of the circuit suggests that it has a fast-
processing speed, making it suitable for applications that require quick and efficient data
processing.

Table 1. Comparison of the previous Full-adders with the Proposed Scheme

Ref. Cells count Area (𝜇𝑚2 ) Latency (clock cycles) Crossover Cost
[14] 48 0.05 3 Coplanar 0.45

[15] 135 0.14 1.25 Multilayer 0.21

10
 [16] 79 0.064 1 Multilayer 0.064

[17] 38 0.02 3 Multilayer 0.18

[10] 45 0.04 0.5 Coplanar 0.01

[11] 59 0.043 1 Coplanar 0.043

[18] 49 0.04 0.75 Coplanar 0.0225

[19] 41 0.04 0.5 Coplanar 0.01

[20] 86 0.1 0.75 Multilayer 0.56

[13] 69 0.05 0.75 Coplanar 0.028

[9] 38 0.02 0.75 Multilayer 0.011

[21] 37 0.039 0.5 Coplanar 0.0097

[22] 37 0.0245 1 Coplanar 0.0245

[12] 20 0.016 0.75 Coplanar 0.009

The suggested 13 0.01 0.5 Coplanar 0.0025

5.6 Comparison of the previous 4-bit QCA RCA with the proposed scheme

Evaluation metrics such as the number of cells, circuit cost, delay, and occupied space
are compared between the suggested 4-bit QCA RCA and the prior designs in this section.
This comparison is seen in Table 2. The suggested 4-bit QCA RCA circuit outperforms
prior designs in terms of various evaluation metrics. Compared to the previous design
[12], the proposed circuit shows improvements of 23% in the number of cells, 16% in
occupied area, 66% in latency, and 90% in circuit cost. These significant improvements in
evaluation metrics demonstrate the efficiency and feasibility of the suggested 4-bit QCA
RCA circuit.

Table 2. Comparison of the previous 4-bit RCA with the Proposed Scheme

Ref. Cells count Area (𝜇𝑚2 ) Latency (clocks) Crossover Cost

[23] 175 0.14 1.75 Coplanar 0.428
[16] 339 0.82 1.75 Multilayer 2.5
[8] 209 0.25 1.25 Coplanar 0.39
[20] 371 0.4 1.5 Multilayer 0.9

11
 [11] 262 0.29 1.75 Coplanar 0.88
[13] 295 0.3 1.5 Coplanar 0.675
[15] 651 1.67 4.25 Multilayer 30.16
[9] 237 0.24 1.5 Multilayer 0.54
[21] 174 0.53 1.25 Coplanar 0.82
[15] 651 1.67 4.25 NR 30.16
[12] 89 0.12 3.75 Coplanar 1.68
The suggested 68 0.1 1.25 Coplanar 0.15625

6. Power dissipation of the suggested Full-adder

QCA Pro [24] is a software tool designed specifically for analyzing energy dissipation
in circuits implemented using QCA technology. QCA Pro specializes in analyzing energy
dissipation, which is crucial for understanding the power characteristics of QCA circuits.
It provides insights into how much energy is consumed during the operation of the QCA
circuit. The tool employs a fast approximation-based method to estimate energy
dissipation. QCA Pro identifies inaccurate cells within the circuit design. Inaccurate cells
may have deviations from ideal behavior, such as imperfect polarization or alignment,
which can affect circuit performance and energy dissipation. It provides evaluation
metrics such as average leakage energy dissipation, average switching energy
dissipation, and total energy dissipation. These metrics help in assessing and optimizing
the energy consumption of QCA circuits. Fig 9 shows a map of the power loss for a
suggested single-bit Full-adder with different energy levels. It displays the varying
power consumption and energy dissipation of the Full-adder circuit at different
operating conditions or inputs, providing a visual representation of the power
characteristics of the circuit. The darker cells in the figure represent higher levels of
consumed energy. Table 4 presents the investigation of energy loss of the suggested
single-bit Full-adder with energy levels (0.5 𝐸𝑘 , 1 𝐸𝑘 , 𝑎𝑛𝑑 1.5 𝐸𝑘 at T = 2 K). The
improvement percentage of suggested single-bit Full-adder compared to [21] is shown in
the last row of Table 4. The proposed Full-adder offers significant improvements,
reducing power consumption by almost 70% compared to previous structures. This is a
substantial progress that will likely result in more efficiency and cost savings.

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 A) Ek=0.5 B) Ek=1 C) Ek=1.5

Fig 9. Map of power loss of suggested single-bit QCA Full-adder circuit A) 0.5 𝐸𝑘 B) 1 𝐸𝑘 C) 1.5 𝐸𝑘

Table 4. Comparison of the previous circuit with the proposed scheme

Average leakage (meV) Average switching (meV) Total energy (meV)

Ref 0.5 𝐸𝑘 1 𝐸𝑘 1.5 𝐸𝑘 0.5 𝐸𝑘 1 𝐸𝑘 1.5 𝐸𝑘 0.5 𝐸𝑘 1 𝐸𝑘 1.5 𝐸𝑘
[2] 15.37 44.87 76.92 61.87 56.03 51.61 77.24 100.9 128.53
[8] 11.12 32.92 58.37 49.1 42.82 36.62 60.22 75.74 94.99
[11] 16.43 51.09 92.6 105.94 92.68 79.61 122.37 143.77 172.21
[25] 14.05 39.32 68.02 50.61 44.67 38.95 64.66 83.99 106.97
[21] 12.95 35.75 61.4 44.24 37.75 31.88 57.2 73.5 93.28
Our design 4.10 11.01 18.55 12.86 10.8 9.19 16.96 21.81 27.64
Improvement 68.4% 69% 70% 71% 71% 71% 70% 70% 70%

7. Conclusion

In this study, a new structure for single-bit Full-adder was suggested in QCA
technology. The proposed Full-adder has 13 cells, occupies an area of 0.01 𝜇𝑚2 , and has
0.5 clock cycles delay. It has a compact design and low area occupancy. Regarding of
evaluation parameters, the suggested Full-adder is superior to the other designs.
Furthermore, the suggested Full-adder was successfully employed in constructing a 4-bit
RCA. The suggested structures simulated by QCADesigner 2.0.3 in coplanar crossover.
This design shows a significant improvement in the evaluation parameters when
compared to the previous plans. It addresses the shortcomings and provides a better
solution in terms of efficiency, functionality, and practicality. Also, we estimated the
energy dissipation of suggested of single-bit Full-adder using the QCAPro tool. The
proposed Full-adder improves power consumption by approximately 70% compared to
previous designs.

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