A Novel Nine Input Majority Gate Design in
Quantum-Dot Cellular Automata
Ankit Kumar, Puneet Agrawal and Bahniman Ghosh
Indian Institute of Technology Kanpur
 blocks of the Majority Gate and the Inverter. Many papers
Abstract— Quantum-Dot Cellular Automata is a technology
that is a feasible alternative to current CMOS technology based
on transistors. In the future, CMOS device scaling results in
leakage and short channel effects which make it unattractive for
use. QCA (Quantum-Dot Cellular Automata) based circuits
shrink the device size to Quantum levels and provide scope for
further improvement and research. Majority Gates and
Inverters mainly form the basic building blocks in QCA circuit
design. The Three-input Majority Gate is most widely used in
logic synthesis and design. In this paper, a Nine-input Majority
Gate is proposed which would find use in multi-bit arithmetic
circuits by reducing overall cell counts and delays. Further, the
proposed design is simulated on QCA designer to prove its
functionality and uses.
Index Terms— Quantum-Dot Cellular Automata, Majority
Gate, QCA logic
I. INTRODUCTION
Presently, all electronic circuits are made and fabricated
using CMOS technology. Current CMOS circuits however,
have serious issue when we scale the device size to quantum
levels. Problems such as those of leakages, short channel
effects, over-heating and signal attenuation are evident in all
these cases.
Keeping in mind the roadmap for development in
electronics, it is believed that the device size would shrink to
seven nm by 2019 [1]. At that stage, transistors will fail to
function properly and thus QCA logic design becomes
important. QCA cells consist of quantum dots in which
electrons can reside. Information is conveyed to the cell based
on the orientation of the electrons. Data flows from one cell to
the other by electrostatic interactions. This type of
information flow does not involve actual electron flow and
thus results in a reduction in the overall power consumption of
the circuit. This feature of QCA circuits enables their usage at
very high frequencies such as in RF circuitry [2-5].
QCA cells conduct data from one to another and thus are
simply used as wires. In digital QCA design, the side-effects
of using metal contacts such as junction capacitances,
parasitic capacitance and high latency delays are all
eliminated. Existing QCA circuits are made using the simple
Manuscript received January 22nd, 2013. This work was supported in part
by the Indian Institute of Technology Kanpur.
Ankit Kumar is with the Indian Institute of Technology Kanpur 208016
India (e-mail: krankit@iitk.ac.in).
Puneet Agrawal is with the Indian Institute of Technology Kanpur
208016 India (e-mail: agrawalp@iitk.ac.in).
Dr. Bahniman Ghosh is a professor of Electrical Engineering at the Indian
Institute of Technology Kanpur 208016 India (e-mail:
bahniman@iitk.ac.in).
have been previously published that describe the usage of
QCA architecture in designing simple adders, multipliers,
ALUs and microprocessors [4, 6-15].
Mainly, three input majority gates have been used to design
digital circuits; however some papers have been published
describing the use of five input majority gates. The usage of
five input gates reduces the fabrication area and the
complexity of the circuit. A Seven-input majority gate has
also been proposed in literature [16]. Using this design, the
paper proposes to further reduce the complexity and the cell
count of the circuit, especially in multi-bit design. Using a
Seven-input gate also allows us to create four input „AND‟
and „OR‟ gates.
In this paper, a new design for a nine input majority gate is
proposed. The simulations of the design are performed on
QCA Designer. The proposed design is a single layer design
and uses only a single clock, thus minimizing the information
processing delay.
II. QCA OVERVIEW
A. Basics
A QCA cell is a device that consists of four quantum wells.
In each cell, two excess electrons reside in two of these wells.
Based on the principle of the minimization of the total system
potential energy, the electrons always take up the diagonally
opposite positions at all times. Thus, two binary states in
which the cell can reside can be used to describe the
information contained in the cell. One position of the two
electrons describes a „1‟ and the other state describes a „0‟ for
showing the two potential levels in normal present-day digital
design as shown in Fig. 1.
Figure 1. The two electronic states for any QCA cell.
III. CLOCKING IN QCA TECHNOLOGY
QCA circuits have a four phase clock unlike CMOS
circuits where there are only two states „high‟ and „low‟. All
the four phases in QCA clocking have a phase shift of 90˚, as
shown in Fig. 2. Power to the QCA circuit comes in the form
of clock itself unlike external power supply as is the case in
CMOS style. The four phases of clock correspond to „switch‟,
„hold‟, „release‟, and „relax‟ [17, 18, 19, 20]. In „switch‟
phase, the barriers are slowly raised and the QCA cells
become polarized according to the state of their input drivers.
In the next „hold‟ phase, the barriers are kept high so that the
cells in that sub array retain their values. During the „release‟
phase, the barriers are lowered and the cells are allowed to
relax to an unpolarized state. In the final „relax‟ phase the
barriers kept on low and the cells remain unpolarized.
V. TYPES OF MAJORITY GATES
The already existing majority gates in the literature are the
Three-input (as shown in Fig.3), the Five-input and the
Seven-input majority gate. The Five-input and Seven-input
gates are discussed in this section now.
The Five-input Majority Gate takes give inputs and
produces an output whose value is what the majority of the
inputs are. The gates are shown in Fig. 6. The logic function
implemented by this gate is:

M (A, B, C, D, E) = ABC + ABD+ ABE+ ACD+ ACE+

ADE+ BCD+ BCE+ BDE+ CDE
Figure 2. Standard QCA clocking scheme.

IV. QCA LOGIC GATES

The most basic logic gate in QCA design is the three input
majority gate as shown in Fig. 3. The gate performs the
following arithmetic operation M (A, B, C) = A.B+B.C+C.A.
By fixing one of the input as „1‟ the gate can be used as an
AND gate and as an OR gate by setting one of the input as „0‟.

Figure 6. Five-input Majority Gate(s).

TABLE 1: TRUTH TABLE OF SEVEN-INPUT MAJORITY GATE BASED ON SUM

OF INPUTS

M (A, B, C) =A.B+A.C+B.C
Σ(A,B,C,D,E,F,G) M(A,B,C,D,E,F,G)
Figure 3. A QCA based Three-input Majority Gate.
0 0
Besides, Majority gates inverter gate also form the major
building block of the QCA based circuits. The most 1 0
commonly used QCA inverters are shown in the Fig. 4.
2 0

3 1

4 1

5 1
Figure 4. Standard QCA inverter designs („A‟ and „B‟) with all cells
numbered.

The first inverter although uses more number of cells, is A Seven-input Majority Gate had been proposed in [16].
more robust and reliable as compared to the other. As The gate is shown in Fig. 7.
mentioned before QCA cell themselves build up the wires in
the QCA circuits. Consecutively placed QCA cells form the
wire passing signal through columbic interaction as shown in
Fig. 5.

Figure 5. A QCA wire.

Figure 7. Seven-input Majority Gate.

 The gate can be used to implement „AND‟ and „OR‟
functions as shown below:
M (A, B, C, D, 0, 0, 0) = A. B. C. D
M (A, B, C, D, 1, 1, 1) = A + B + C + D
Using such a gate can reduce the cell count and the circuit
size in complex multi-bit QCA circuitry and help in effective
utilization of substrate space.
VI. PROPOSED NINE-INPUT MAJORITY GATE
In this section, the proposed Nine-input Majority Gate is
described and explained. It is a single layer design and does
not require cells to be fabricated in multiple layers for proper
functioning. The gate is very useful in multi-bit design of
adders and ALUs which currently are very complex to
simulate and design. The designed Nine-input gate is as
shown in Fig. 8.
The logic truth table for this gate is shown as in Table I.
The gate can also be used in a variety of QCA circuits
including those of decoders, multipliers and multiplexers
[6-15, 21, 22].
Figure 8. Nine-Input Majority Gate with all its inputs numbered.
Figure 10. „OR‟ state simulation.
The simulations of the above design are performed on QCA
Designer. The gate is simulated by fixing some of the
polarization states of the input cells. This is done because the
wiring of the QCA gate requires a multi-layer design and it is
difficult to otherwise visualize the outputs.
VII. SIMULATIONS
The design is simulated on QCA Designer, reliable open-
source software available on the internet. The system states
that cause the „AND‟ and „OR‟ are shown in Fig. 9 and 11.
The „OR‟ state is simulated by keeping some of the inputs
fixed to „1‟ and the „AND‟ state is simulated by fixing the
polarization state of some of the inputs to „0‟. The results are
shown in Fig. 10 and 12. The „OR‟ state output is high when
any one of the inputs is high and the „AND‟ state output is
high when all the given inputs are high, else low.
M (A, B, C, D, E, 0, 0, 0, 0) = A.B.C.D.E
M (A, B, C, D, E, 1, 1, 1, 1) = A + B + C + D + E
Figure 9. Nine-Input Majority Gate states for „OR‟ simulations.

Figure 11. Nine-Input Majority Gate states for „AND‟ simulations.
Figure 12. „AND‟ state simulation.
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VIII. CONCLUSION
The Nine-Input Majority gate is a novel QCA device
architecture and can be used to reduce complexity of QCA
circuits. Many works have been published before making the
use of three and five input Majority Gates and the Nine-input
gate is a significant addition to them.
Various logical device and circuitry of decoders, ALUs,
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IX. ACKNOWLEDGEMENTS
Finally the publication of this work has been possible by
the generous funds available to the author through the Dean of
Academic Affairs, Dean of Resource Planning and
Generation, Dean of Research and Development and Head of
the Department of Electrical Engineering, at the Indian
Institute of Technology Kanpur, India.
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